diff --git a/Semaine_7/DHT11_UART/IP/verilog/dht11_interface.v b/Semaine_7/DHT11_UART/IP/verilog/dht11_interface.v
index 819b4bc..c7c20de 100644
--- a/Semaine_7/DHT11_UART/IP/verilog/dht11_interface.v
+++ b/Semaine_7/DHT11_UART/IP/verilog/dht11_interface.v
@@ -107,7 +107,7 @@ module dht11_interface #(
 
                 timer <= timer + 1;
 
-                if (sig_in == 0 && timer > 2) begin
+                if (sig_in == 0) begin
                        
                     state <= RESPONSE_LOW;
                     timer <= 0;
@@ -119,7 +119,7 @@ module dht11_interface #(
                 o_state <= state;
                 timer <= timer + 1;
 
-                if (sig_in == 1 && timer > 2) begin
+                if (sig_in == 1 ) begin
                     
                     timer <= 0;
                     state <= RESPONSE_HIGH;
@@ -159,7 +159,7 @@ module dht11_interface #(
 
                     bit_index <= bit_index + 1;
 
-                    if (bit_index == 39) begin 
+                    if (bit_index == 40) begin 
                         state <= DONE;
                     end else begin
                         state <= READ_BITS_LOW;