verlan/Verilog_Louis
1
0
Fork 0
forked from tanchou/Verilog
Code Pull Requests Activity

Refactor LED handling in fpga_wifi_led module and remove obsolete readSerial.py script

Browse Source
This commit is contained in:
Gamenight77
2025-05-28 09:26:09 +02:00
parent 47de4a955b
commit 502999b159
3 changed files with 34 additions and 34 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
Semaine_7/ESP32/leds_commands/src/verilog/fpga_wifi_led.v
View File

@@ -22,7 +22,7 @@ module fpga_wifi_led (
wire tx_fifo_full;
// === SIGNAUX INTERNES ===
reg [5:0] leds_reg;
reg [3:0] leds_reg;
reg [1:0] state;
reg [7:0] received_byte;
@@ -59,11 +59,13 @@ module fpga_wifi_led (
);
// === ASSIGNATION DES LEDS ===
assign o_leds = ~leds_reg;
assign o_leds [3:0] = ~leds_reg;
assign o_leds[5] = o_tx;
assign o_leds[4] = i_rx;
// === INITIALISATION ===
initial begin
leds_reg = 6'b000000;
leds_reg = 4'b0000;
state = IDLE;
rx_rd_en = 0;
tx_wr_en = 0;
@@ -110,7 +112,7 @@ module fpga_wifi_led (
state <= SEND_RESPONSE;
end else begin
// Commande non reconnue, éteindre toutes les LEDs
leds_reg <= 6'b000000;
leds_reg[2:0] <= 3'b111;
state <= IDLE;
end
end