From 589c36ed8315f70b2c73837e2d32ec5621919d3d Mon Sep 17 00:00:00 2001 From: Gamenight77 Date: Mon, 5 May 2025 14:52:01 +0200 Subject: [PATCH] Loopback ne fonctionne pas --- .../UART/constraints/top_uart_loopback.cst | 19 ++++++ Semaine_4/UART/scripts/build.bat | 24 +++---- .../UART/src/verilog/top_uart_loopback.v | 66 +++++++++++++++++++ .../UART/tests/Python/uart_loopback_test.py | 43 ++++++++++++ 4 files changed, 140 insertions(+), 12 deletions(-) create mode 100644 Semaine_4/UART/constraints/top_uart_loopback.cst create mode 100644 Semaine_4/UART/src/verilog/top_uart_loopback.v create mode 100644 Semaine_4/UART/tests/Python/uart_loopback_test.py diff --git a/Semaine_4/UART/constraints/top_uart_loopback.cst b/Semaine_4/UART/constraints/top_uart_loopback.cst new file mode 100644 index 0000000..e1fb732 --- /dev/null +++ b/Semaine_4/UART/constraints/top_uart_loopback.cst @@ -0,0 +1,19 @@ +IO_LOC "rx" 70; +IO_PORT "rx" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8; +IO_LOC "tx" 69; +IO_PORT "tx" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8; +IO_LOC "clk" 4; +IO_PORT "clk" PULL_MODE=UP BANK_VCCIO=1.8; + +IO_LOC "leds[0]" 15; +IO_PORT "leds[0]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8; +IO_LOC "leds[1]" 16; +IO_PORT "leds[1]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8; +IO_LOC "leds[2]" 17; +IO_PORT "leds[2]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8; +IO_LOC "leds[3]" 18; +IO_PORT "leds[3]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8; +IO_LOC "leds[4]" 19; +IO_PORT "leds[4]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8; +IO_LOC "leds[5]" 20; +IO_PORT "leds[5]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8; \ No newline at end of file diff --git a/Semaine_4/UART/scripts/build.bat b/Semaine_4/UART/scripts/build.bat index c0647db..aed8469 100644 --- a/Semaine_4/UART/scripts/build.bat +++ b/Semaine_4/UART/scripts/build.bat @@ -1,29 +1,29 @@ @echo off setlocal +rem === Aller à la racine du projet === +cd /d %~dp0\.. + rem === Config de base === set DEVICE=GW2AR-LV18QN88C8/I7 set BOARD=tangnano20k set TOP=top_uart_loopback set CST_FILE=%TOP%.cst -set SRC_FILE=../src/verilog/%TOP%.v -set JSON_FILE=%TOP%.json -set PNR_JSON=pnr_%TOP%.json -set BITSTREAM=%TOP%.fs +set JSON_FILE=runs/%TOP%.json +set PNR_JSON=runs/pnr_%TOP%.json +set BITSTREAM=runs/%TOP%.fs rem === Créer le dossier runs si nécessaire === -if not exist ../runs ( - mkdir ../runs +if not exist runs ( + mkdir runs ) -cd ../runs - echo === Étape 1 : Synthèse avec Yosys === -yosys -p "read_verilog %SRC_FILE%; synth_gowin -json %JSON_FILE%" +yosys -p "read_verilog -sv src/verilog/%TOP%.v src/verilog/uart_rx.v src/verilog/uart_tx.v; synth_gowin -top %TOP% -json %JSON_FILE%" if errorlevel 1 goto error echo === Étape 2 : Placement & Routage avec nextpnr-himbaechel === -nextpnr-himbaechel --json %JSON_FILE% --write %PNR_JSON% --device %DEVICE% --vopt cst=../constraints/%CST_FILE% --vopt family=GW2A-18C +nextpnr-himbaechel --json %JSON_FILE% --write %PNR_JSON% --device %DEVICE% --vopt cst=constraints/%CST_FILE% --vopt family=GW2A-18C if errorlevel 1 goto error echo === Étape 3 : Packing avec gowin_pack === @@ -34,11 +34,11 @@ echo === Étape 4 : Flash avec openFPGALoader === openFPGALoader -b %BOARD% %BITSTREAM% if errorlevel 1 goto error -echo === ✅ Compilation et flash réussis === +echo === Compilation et flash réussis === goto end :error -echo === ❌ Une erreur est survenue === +echo === Une erreur est survenue === :end endlocal diff --git a/Semaine_4/UART/src/verilog/top_uart_loopback.v b/Semaine_4/UART/src/verilog/top_uart_loopback.v new file mode 100644 index 0000000..f71f6c2 --- /dev/null +++ b/Semaine_4/UART/src/verilog/top_uart_loopback.v @@ -0,0 +1,66 @@ +module top_uart_loopback ( + input wire clk, // 27 MHz + input wire rx, + output wire tx, + output reg [5:0] leds +); + + wire rx_received; + wire [7:0] rx_data; + reg [7:0] tx_data; + reg tx_enable; + + wire tx_ready; + + initial begin + leds = 6'b000000; // Initialiser les LEDs à 0 + end + + // === UART RX === + uart_rx uart_rx_inst ( + .clk(clk), + .rst_p(1'b0), + .rx_pin(rx), + .rx_received(rx_received), + .rx_enable(1'b1), + .rx_data(rx_data) + ); + + // === UART TX === + uart_tx uart_tx_inst ( + .clk(clk), + .rst_p(1'b0), + .data(tx_data), + .tx_enable(tx_enable), + .tx_ready(tx_ready), + .tx(tx) + ); + + // === FSM pour déclencher la transmission === + localparam IDLE = 0, SEND = 1; + reg state = IDLE; + + always @(posedge clk) begin + case (state) + IDLE: begin + tx_enable <= 0; + if (rx_received && tx_ready) begin + tx_data <= rx_data; + tx_enable <= 1; + state <= SEND; + leds[0] <= 1; + leds[5:1] <= 0; + end + end + + SEND: begin + tx_enable <= 0; + state <= IDLE; + + leds[0] <= 0; // LED 0 allumée pour indiquer la réception + leds[1] <= 1; // LED 1 éteinte pour indiquer l'attente de transmission + end + endcase + end + +endmodule diff --git a/Semaine_4/UART/tests/Python/uart_loopback_test.py b/Semaine_4/UART/tests/Python/uart_loopback_test.py new file mode 100644 index 0000000..ca96240 --- /dev/null +++ b/Semaine_4/UART/tests/Python/uart_loopback_test.py @@ -0,0 +1,43 @@ +import serial +import time + +# À adapter selon ton système +PORT = 'COM7' # ex: COM3 sur Windows ou /dev/ttyUSB0 sur Linux +BAUDRATE = 115200 +TIMEOUT = 3 # en secondes + +def main(): + try: + with serial.Serial(PORT, BAUDRATE, timeout=TIMEOUT) as ser: + print(f"[INFO] Connecté à {PORT} à {BAUDRATE} bauds.") + print("Tape un nombre entre 0 et 255. Ctrl+C pour quitter.\n") + + while True: + user_input = input("Nombre à envoyer (0-255) : ") + + if not user_input.isdigit(): + print("⚠️ Entrée invalide. Tape un entier entre 0 et 255.") + continue + + value = int(user_input) + if value < 0 or value >= 255: + print("⚠️ Valeur hors limites.") + continue + + byte = bytes([value]) + ser.write(byte) + print(f"[TX] Envoyé : {value} (0x{value:02X})") + + time.sleep(0.01) # petite pause si nécessaire + + rx = ser.read(1) + if rx: + print(f"[RX] Reçu : {int.from_bytes(rx, 'little')} (0x{rx.hex()})\n") + else: + print("⚠️ Aucun octet reçu (timeout ?)\n") + + except serial.SerialException as e: + print(f"[ERREUR] Port série : {e}") + +if __name__ == "__main__": + main()