diff --git a/Semaine_1/Capteur_recule_bidirectionel/Ultrasonic/ultrasonic_fpga.v b/Semaine_1/Capteur_recule_bidirectionel/Ultrasonic/ultrasonic_fpga.v
index be1c6af..88b3592 100644
--- a/Semaine_1/Capteur_recule_bidirectionel/Ultrasonic/ultrasonic_fpga.v
+++ b/Semaine_1/Capteur_recule_bidirectionel/Ultrasonic/ultrasonic_fpga.v
@@ -34,7 +34,7 @@ module ultrasonic_fpga #(
     reg [31:0] wait_counter;
 
 
-    always @(posedge clk) begin
+    always @(posedge clk) begin // FSM
         
         case (state)
             IDLE: begin