From 5f3568ff9bf098c94c08196d1d86a901d708f926 Mon Sep 17 00:00:00 2001 From: Gamenight77 Date: Tue, 22 Apr 2025 14:40:12 +0200 Subject: [PATCH] Enhance ultrasonic_fpga module: add comment to clarify FSM behavior in the Verilog file --- .../Capteur_recule_bidirectionel/Ultrasonic/ultrasonic_fpga.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Semaine_1/Capteur_recule_bidirectionel/Ultrasonic/ultrasonic_fpga.v b/Semaine_1/Capteur_recule_bidirectionel/Ultrasonic/ultrasonic_fpga.v index be1c6af..88b3592 100644 --- a/Semaine_1/Capteur_recule_bidirectionel/Ultrasonic/ultrasonic_fpga.v +++ b/Semaine_1/Capteur_recule_bidirectionel/Ultrasonic/ultrasonic_fpga.v @@ -34,7 +34,7 @@ module ultrasonic_fpga #( reg [31:0] wait_counter; - always @(posedge clk) begin + always @(posedge clk) begin // FSM case (state) IDLE: begin