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forked from tanchou/Verilog

Refactor UART testbench and top-level modules; remove old testbench files, enhance UART communication in top_ultrason_uart, and implement LED control via UART in top_led_uart. Add Python scripts for UART communication and data reading.

This commit is contained in:
Gamenight77
2025-04-17 18:00:54 +02:00
parent 897f829e40
commit 65cf0e8232
13 changed files with 142 additions and 39776 deletions

View File

@@ -5,7 +5,7 @@ module ultrasonic_fpga #(
input wire start,
inout wire sig, // Broche bidirectionnelle vers le capteur
output reg [15:0] distance, // Distance mesurée en cm
output reg [2:0] state
output reg [2:0] state = IDLE
);
reg [15:0] trig_counter;
reg [31:0] echo_counter;