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forked from tanchou/Verilog

Refactor UART testbench and top-level modules; remove old testbench files, enhance UART communication in top_ultrason_uart, and implement LED control via UART in top_led_uart. Add Python scripts for UART communication and data reading.

This commit is contained in:
Gamenight77
2025-04-17 18:00:54 +02:00
parent 897f829e40
commit 65cf0e8232
13 changed files with 142 additions and 39776 deletions

View File

@@ -2,7 +2,7 @@ module top_ultrason_uart(
input wire clk,
input wire start,
inout wire sig,
output wire tx,
output wire tx
);
parameter CLK_FREQ = 27_000_000;
@@ -41,15 +41,34 @@ module top_ultrason_uart(
.tx(tx)
);
always @(posedge clk) begin
if (state_sensor == 3'd6) begin // Lorsque la mesure est terminée, préparer les données
tx_data <= distance;
tx_start <= 1;
reg [31:0] wait_counter;
reg [1:0] state;
localparam WAIT_NEXT_CYCLES = (CLK_FREQ / 1000) * 100; // 60 ms
end else begin
tx_start <= 0;
end
localparam START = 2'd0;
localparam WAIT = 2'd1;
always @(posedge clk) begin
case(state)
START:begin
if (state_sensor == 3'd6) begin // Lorsque la mesure est terminée, préparer les données
tx_data <= distance;
tx_start <= 1;
state <= WAIT;
end
end
WAIT:begin
tx_start <= 0;
wait_counter <= wait_counter + 1;
if (wait_counter >= WAIT_NEXT_CYCLES) begin
state <= START;
wait_counter <= 0;
end
end
endcase
end
endmodule