forked from tanchou/Verilog
Refactor UART testbench and top-level modules; remove old testbench files, enhance UART communication in top_ultrason_uart, and implement LED control via UART in top_led_uart. Add Python scripts for UART communication and data reading.
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@@ -2,7 +2,7 @@ module top_ultrason_uart(
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input wire clk,
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input wire start,
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inout wire sig,
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output wire tx,
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output wire tx
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);
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parameter CLK_FREQ = 27_000_000;
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@@ -41,15 +41,34 @@ module top_ultrason_uart(
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.tx(tx)
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);
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always @(posedge clk) begin
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if (state_sensor == 3'd6) begin // Lorsque la mesure est terminée, préparer les données
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tx_data <= distance;
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tx_start <= 1;
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reg [31:0] wait_counter;
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reg [1:0] state;
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localparam WAIT_NEXT_CYCLES = (CLK_FREQ / 1000) * 100; // 60 ms
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end else begin
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tx_start <= 0;
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end
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localparam START = 2'd0;
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localparam WAIT = 2'd1;
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always @(posedge clk) begin
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case(state)
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START:begin
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if (state_sensor == 3'd6) begin // Lorsque la mesure est terminée, préparer les données
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tx_data <= distance;
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tx_start <= 1;
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state <= WAIT;
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end
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end
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WAIT:begin
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tx_start <= 0;
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wait_counter <= wait_counter + 1;
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if (wait_counter >= WAIT_NEXT_CYCLES) begin
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state <= START;
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wait_counter <= 0;
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end
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end
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endcase
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end
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endmodule
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