Refactor UART testbench and top-level modules; remove old testbench files, enhance UART communication in top_ultrason_uart, and implement LED control via UART in top_led_uart. Add Python scripts for UART communication and data reading.

Semaine 1/Capteur_recule_bidirectionel/Ultrasonic/ultrasonic_fpga.v

@@ -5,7 +5,7 @@ module ultrasonic_fpga #(
     input  wire start,
     inout  wire sig,                // Broche bidirectionnelle vers le capteur
     output reg [15:0] distance,  // Distance mesurée en cm
-    output reg [2:0] state
+    output reg [2:0] state = IDLE
 );
     reg [15:0] trig_counter;
     reg [31:0] echo_counter;

Semaine 1/Python_UART/led_uart.py

@@ -0,0 +1,30 @@
+import serial
+import time
+
+# Ouvre le port série (à adapter si nécessaire)
+ser = serial.Serial('COM6', 115200, timeout=0.5)  # timeout non bloquant
+
+print("Entrez un chiffre entre 0 et 5 pour toggler une LED.")
+
+try:
+    while True:
+        user_input = input("> ")
+        if user_input.isdigit() and 0 <= int(user_input) <= 64:
+            value = int(user_input)
+            ser.write(bytes([value]))  # envoie en binaire brut
+            print(f"Envoyé : {value} -> {value:08b}")
+
+            # Lecture de la réponse UART (1 octet)
+            response = ser.read(1)
+            if response:
+                led_state = response[0]
+                print(f"État reçu du FPGA : {led_state:08b}")
+            else:
+                print("⚠️ Aucune réponse reçue.")
+        else:
+            print("Veuillez entrer un chiffre entre 0 et 63.")
+
+except KeyboardInterrupt:
+    print("\nFermeture.")
+finally:
+    ser.close()

Semaine 1/Python_UART/read_rx.py

@@ -0,0 +1,15 @@
+import serial
+import time
+
+ser = serial.Serial('COM6', 115200) 
+ser.timeout = 1 
+
+# Boucle pour lire les données du port série
+while True:
+    if ser.in_waiting > 0:
+        data = ser.read(1) 
+        
+        distance = int.from_bytes(data, byteorder='little')
+        print(f'Distance reçue : {distance} cm')
+
+ser.close()

Semaine 1/UART/top_led_uart.v

@@ -0,0 +1,61 @@
+module top_led_uart(
+    input wire clk,
+    input wire rx,
+    output wire tx,
+    output reg [5:0] leds
+);
+    wire [7:0] data_out;
+    wire valid;
+    reg start_tx = 0;
+    reg [7:0] data_in = 0;
+
+    top_uart_rx_tx uart (
+        .clk(clk),
+        .start(start_tx),
+        .data_in(data_in),
+        .rx(rx),
+        .data_out(data_out),
+        .valid(valid),
+        .tx(tx)
+    );
+
+    reg [1:0] state = 0;
+    localparam IDLE = 2'd0;
+    localparam TOGGLE = 2'd1;
+    localparam SEND_BACK = 2'd2;
+
+    always @(posedge clk) begin
+        case (state)
+            INIT: begin
+                leds <= 6'b000000; 
+                start_tx <= 0;
+                if (valid) begin
+                    
+                    leds <= data_out[5:0];
+                    state <= SEND_BACK;
+                    
+                end
+            end
+            IDLE: begin
+                start_tx <= 0;
+                if (valid) begin
+                    
+                    leds <= data_out[5:0];
+                    state <= SEND_BACK;
+                    
+                end
+            end
+
+            SEND_BACK: begin
+                data_in <= data_out;
+                start_tx <= 1;
+                state <= TOGGLE;
+            end
+
+            TOGGLE: begin
+                start_tx <= 0;
+                state <= IDLE;
+            end
+        endcase
+    end
+endmodule

Semaine 1/UART/top_uart_tx_tb

@@ -1,408 +0,0 @@
-#! 
-:ivl_version "13.0 (devel)" "(s20250103-31-g7e238e7ca-dirty)";
-:ivl_delay_selection "TYPICAL";
-:vpi_time_precision - 12;
-:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\system.vpi";
-:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\vhdl_sys.vpi";
-:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\vhdl_textio.vpi";
-:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\v2005_math.vpi";
-:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\va_math.vpi";
-S_00000229acd190a0 .scope module, "tb_top_uart_rx_tx" "tb_top_uart_rx_tx" 2 3;
- .timescale -9 -12;
-P_00000229accd6e80 .param/l "BAUD_RATE" 0 2 6, +C4<00000000000000011100001000000000>;
-P_00000229accd6eb8 .param/l "CLK_FREQ" 0 2 5, +C4<00000001100110111111110011000000>;
-L_00000229acd19630 .functor BUFZ 1, v00000229acd79f10_0, C4<0>, C4<0>, C4<0>;
-v00000229acd79b50_0 .var "clk", 0 0;
-v00000229acd790b0_0 .var "data_in", 7 0;
-v00000229acd79bf0_0 .net "data_out", 7 0, v00000229acd0de70_0;  1 drivers
-v00000229acd79d30_0 .net "rx", 0 0, L_00000229acd19630;  1 drivers
-v00000229acd79150_0 .var "start", 0 0;
-v00000229acd7ad40_0 .net "tx", 0 0, v00000229acd79f10_0;  1 drivers
-v00000229acd7bd80_0 .net "valid", 0 0, v00000229acd79470_0;  1 drivers
-E_00000229accfc720 .event anyedge, v00000229acd79470_0;
-S_00000229acd19230 .scope module, "uut" "top_uart_rx_tx" 2 21, 3 1 0, S_00000229acd190a0;
- .timescale 0 0;
-    .port_info 0 /INPUT 1 "clk";
-    .port_info 1 /INPUT 1 "start";
-    .port_info 2 /INPUT 8 "data_in";
-    .port_info 3 /INPUT 1 "rx";
-    .port_info 4 /OUTPUT 8 "data_out";
-    .port_info 5 /OUTPUT 1 "valid";
-    .port_info 6 /OUTPUT 1 "tx";
-P_00000229accd6c60 .param/l "BAUD_RATE" 0 3 12, +C4<00000000000000011100001000000000>;
-P_00000229accd6c98 .param/l "CLK_FREQ" 0 3 11, +C4<00000001100110111111110011000000>;
-v00000229acd79830_0 .net "clk", 0 0, v00000229acd79b50_0;  1 drivers
-v00000229acd79650_0 .net "data_in", 7 0, v00000229acd790b0_0;  1 drivers
-v00000229acd79ab0_0 .net "data_out", 7 0, v00000229acd0de70_0;  alias, 1 drivers
-v00000229acd79fb0_0 .net "rx", 0 0, L_00000229acd19630;  alias, 1 drivers
-v00000229acd796f0_0 .net "start", 0 0, v00000229acd79150_0;  1 drivers
-v00000229acd79970_0 .net "tx", 0 0, v00000229acd79f10_0;  alias, 1 drivers
-v00000229acd79790_0 .net "valid", 0 0, v00000229acd79470_0;  alias, 1 drivers
-S_00000229acd193c0 .scope module, "rx_instance" "uart_rx" 3 27, 4 1 0, S_00000229acd19230;
- .timescale -9 -12;
-    .port_info 0 /INPUT 1 "clk";
-    .port_info 1 /INPUT 1 "rx";
-    .port_info 2 /OUTPUT 8 "data";
-    .port_info 3 /OUTPUT 1 "valid";
-    .port_info 4 /OUTPUT 1 "ready";
-P_00000229acd0dce0 .param/l "BAUD_RATE" 0 4 10, +C4<00000000000000011100001000000000>;
-P_00000229acd0dd18 .param/l "BIT_PERIOD" 1 4 12, +C4<00000000000000000000000011101010>;
-P_00000229acd0dd50 .param/l "CLK_FREQ" 0 4 9, +C4<00000001100110111111110011000000>;
-P_00000229acd0dd88 .param/l "DATA" 1 4 16, C4<10>;
-P_00000229acd0ddc0 .param/l "IDLE" 1 4 14, C4<00>;
-P_00000229acd0ddf8 .param/l "START" 1 4 15, C4<01>;
-P_00000229acd0de30 .param/l "STOP" 1 4 17, C4<11>;
-v00000229acd00f00_0 .var "bit_index", 3 0;
-v00000229acd00fa0_0 .net "clk", 0 0, v00000229acd79b50_0;  alias, 1 drivers
-v00000229accd6a10_0 .var "clk_count", 15 0;
-v00000229acd0de70_0 .var "data", 7 0;
-v00000229acd0df10_0 .var "ready", 0 0;
-v00000229acd79dd0_0 .net "rx", 0 0, L_00000229acd19630;  alias, 1 drivers
-v00000229acd798d0_0 .var "rx_data", 7 0;
-v00000229acd79290_0 .var "state", 1 0;
-v00000229acd79470_0 .var "valid", 0 0;
-E_00000229accfc4e0 .event posedge, v00000229acd00fa0_0;
-S_00000229acd0dfb0 .scope module, "tx_instance" "uart_tx" 3 17, 5 1 0, S_00000229acd19230;
- .timescale -9 -12;
-    .port_info 0 /INPUT 1 "clk";
-    .port_info 1 /INPUT 1 "start";
-    .port_info 2 /INPUT 8 "data";
-    .port_info 3 /OUTPUT 1 "tx";
-    .port_info 4 /OUTPUT 1 "busy";
-P_00000229acbec9b0 .param/l "BAUD_RATE" 0 5 10, +C4<00000000000000011100001000000000>;
-P_00000229acbec9e8 .param/l "BIT_PERIOD" 1 5 11, +C4<00000000000000000000000011101010>;
-P_00000229acbeca20 .param/l "CLK_FREQ" 0 5 9, +C4<00000001100110111111110011000000>;
-P_00000229acbeca58 .param/l "DATA" 1 5 15, C4<10>;
-P_00000229acbeca90 .param/l "IDLE" 1 5 13, C4<00>;
-P_00000229acbecac8 .param/l "START" 1 5 14, C4<01>;
-P_00000229acbecb00 .param/l "STOP" 1 5 16, C4<11>;
-v00000229acd79a10_0 .var "bit_index", 3 0;
-v00000229acd793d0_0 .var "busy", 0 0;
-v00000229acd79e70_0 .net "clk", 0 0, v00000229acd79b50_0;  alias, 1 drivers
-v00000229acd79510_0 .var "clk_count", 15 0;
-v00000229acd79c90_0 .net "data", 7 0, v00000229acd790b0_0;  alias, 1 drivers
-v00000229acd79330_0 .net "start", 0 0, v00000229acd79150_0;  alias, 1 drivers
-v00000229acd795b0_0 .var "state", 1 0;
-v00000229acd79f10_0 .var "tx", 0 0;
-v00000229acd791f0_0 .var "tx_data", 7 0;
-    .scope S_00000229acd0dfb0;
-T_0 ;
-    %pushi/vec4 1, 0, 1;
-    %store/vec4 v00000229acd79f10_0, 0, 1;
-    %pushi/vec4 0, 0, 1;
-    %store/vec4 v00000229acd793d0_0, 0, 1;
-    %pushi/vec4 0, 0, 2;
-    %store/vec4 v00000229acd795b0_0, 0, 2;
-    %pushi/vec4 0, 0, 4;
-    %store/vec4 v00000229acd79a10_0, 0, 4;
-    %pushi/vec4 0, 0, 16;
-    %store/vec4 v00000229acd79510_0, 0, 16;
-    %pushi/vec4 0, 0, 8;
-    %store/vec4 v00000229acd791f0_0, 0, 8;
-    %end;
-    .thread T_0;
-    .scope S_00000229acd0dfb0;
-T_1 ;
-    %wait E_00000229accfc4e0;
-    %load/vec4 v00000229acd795b0_0;
-    %dup/vec4;
-    %pushi/vec4 0, 0, 2;
-    %cmp/u;
-    %jmp/1 T_1.0, 6;
-    %dup/vec4;
-    %pushi/vec4 1, 0, 2;
-    %cmp/u;
-    %jmp/1 T_1.1, 6;
-    %dup/vec4;
-    %pushi/vec4 2, 0, 2;
-    %cmp/u;
-    %jmp/1 T_1.2, 6;
-    %dup/vec4;
-    %pushi/vec4 3, 0, 2;
-    %cmp/u;
-    %jmp/1 T_1.3, 6;
-    %jmp T_1.4;
-T_1.0 ;
-    %pushi/vec4 0, 0, 1;
-    %assign/vec4 v00000229acd793d0_0, 0;
-    %pushi/vec4 1, 0, 1;
-    %assign/vec4 v00000229acd79f10_0, 0;
-    %load/vec4 v00000229acd79330_0;
-    %flag_set/vec4 9;
-    %flag_get/vec4 9;
-    %jmp/0 T_1.7, 9;
-    %load/vec4 v00000229acd793d0_0;
-    %nor/r;
-    %and;
-T_1.7;
-    %flag_set/vec4 8;
-    %jmp/0xz  T_1.5, 8;
-    %load/vec4 v00000229acd79c90_0;
-    %assign/vec4 v00000229acd791f0_0, 0;
-    %pushi/vec4 0, 0, 4;
-    %assign/vec4 v00000229acd79a10_0, 0;
-    %pushi/vec4 0, 0, 16;
-    %assign/vec4 v00000229acd79510_0, 0;
-    %pushi/vec4 1, 0, 1;
-    %assign/vec4 v00000229acd793d0_0, 0;
-    %pushi/vec4 1, 0, 2;
-    %assign/vec4 v00000229acd795b0_0, 0;
-T_1.5 ;
-    %jmp T_1.4;
-T_1.1 ;
-    %load/vec4 v00000229acd79510_0;
-    %pad/u 32;
-    %cmpi/u 233, 0, 32;
-    %jmp/0xz  T_1.8, 5;
-    %load/vec4 v00000229acd79510_0;
-    %addi 1, 0, 16;
-    %assign/vec4 v00000229acd79510_0, 0;
-    %pushi/vec4 0, 0, 1;
-    %assign/vec4 v00000229acd79f10_0, 0;
-    %jmp T_1.9;
-T_1.8 ;
-    %pushi/vec4 2, 0, 2;
-    %assign/vec4 v00000229acd795b0_0, 0;
-    %pushi/vec4 0, 0, 16;
-    %assign/vec4 v00000229acd79510_0, 0;
-T_1.9 ;
-    %jmp T_1.4;
-T_1.2 ;
-    %load/vec4 v00000229acd79510_0;
-    %pad/u 32;
-    %cmpi/u 233, 0, 32;
-    %jmp/0xz  T_1.10, 5;
-    %load/vec4 v00000229acd79510_0;
-    %addi 1, 0, 16;
-    %assign/vec4 v00000229acd79510_0, 0;
-    %jmp T_1.11;
-T_1.10 ;
-    %load/vec4 v00000229acd79a10_0;
-    %pad/u 32;
-    %cmpi/u 8, 0, 32;
-    %jmp/0xz  T_1.12, 5;
-    %load/vec4 v00000229acd791f0_0;
-    %load/vec4 v00000229acd79a10_0;
-    %part/u 1;
-    %assign/vec4 v00000229acd79f10_0, 0;
-    %load/vec4 v00000229acd79a10_0;
-    %addi 1, 0, 4;
-    %assign/vec4 v00000229acd79a10_0, 0;
-    %pushi/vec4 0, 0, 16;
-    %assign/vec4 v00000229acd79510_0, 0;
-    %jmp T_1.13;
-T_1.12 ;
-    %pushi/vec4 3, 0, 2;
-    %assign/vec4 v00000229acd795b0_0, 0;
-T_1.13 ;
-T_1.11 ;
-    %jmp T_1.4;
-T_1.3 ;
-    %pushi/vec4 1, 0, 1;
-    %assign/vec4 v00000229acd79f10_0, 0;
-    %load/vec4 v00000229acd79510_0;
-    %pad/u 32;
-    %cmpi/u 233, 0, 32;
-    %jmp/0xz  T_1.14, 5;
-    %load/vec4 v00000229acd79510_0;
-    %addi 1, 0, 16;
-    %assign/vec4 v00000229acd79510_0, 0;
-    %jmp T_1.15;
-T_1.14 ;
-    %pushi/vec4 0, 0, 16;
-    %assign/vec4 v00000229acd79510_0, 0;
-    %pushi/vec4 0, 0, 1;
-    %assign/vec4 v00000229acd793d0_0, 0;
-    %pushi/vec4 0, 0, 2;
-    %assign/vec4 v00000229acd795b0_0, 0;
-T_1.15 ;
-    %jmp T_1.4;
-T_1.4 ;
-    %pop/vec4 1;
-    %jmp T_1;
-    .thread T_1;
-    .scope S_00000229acd193c0;
-T_2 ;
-    %pushi/vec4 0, 0, 1;
-    %store/vec4 v00000229acd79470_0, 0, 1;
-    %pushi/vec4 1, 0, 1;
-    %store/vec4 v00000229acd0df10_0, 0, 1;
-    %pushi/vec4 0, 0, 2;
-    %store/vec4 v00000229acd79290_0, 0, 2;
-    %pushi/vec4 0, 0, 8;
-    %store/vec4 v00000229acd798d0_0, 0, 8;
-    %end;
-    .thread T_2;
-    .scope S_00000229acd193c0;
-T_3 ;
-    %wait E_00000229accfc4e0;
-    %load/vec4 v00000229acd79290_0;
-    %dup/vec4;
-    %pushi/vec4 0, 0, 2;
-    %cmp/u;
-    %jmp/1 T_3.0, 6;
-    %dup/vec4;
-    %pushi/vec4 1, 0, 2;
-    %cmp/u;
-    %jmp/1 T_3.1, 6;
-    %dup/vec4;
-    %pushi/vec4 2, 0, 2;
-    %cmp/u;
-    %jmp/1 T_3.2, 6;
-    %dup/vec4;
-    %pushi/vec4 3, 0, 2;
-    %cmp/u;
-    %jmp/1 T_3.3, 6;
-    %jmp T_3.4;
-T_3.0 ;
-    %pushi/vec4 1, 0, 1;
-    %assign/vec4 v00000229acd0df10_0, 0;
-    %load/vec4 v00000229acd79dd0_0;
-    %nor/r;
-    %flag_set/vec4 8;
-    %jmp/0xz  T_3.5, 8;
-    %pushi/vec4 1, 0, 2;
-    %assign/vec4 v00000229acd79290_0, 0;
-    %pushi/vec4 0, 0, 16;
-    %assign/vec4 v00000229accd6a10_0, 0;
-    %pushi/vec4 0, 0, 4;
-    %assign/vec4 v00000229acd00f00_0, 0;
-    %pushi/vec4 0, 0, 1;
-    %assign/vec4 v00000229acd79470_0, 0;
-    %pushi/vec4 0, 0, 1;
-    %assign/vec4 v00000229acd0df10_0, 0;
-T_3.5 ;
-    %jmp T_3.4;
-T_3.1 ;
-    %load/vec4 v00000229accd6a10_0;
-    %pad/u 32;
-    %cmpi/u 350, 0, 32;
-    %jmp/0xz  T_3.7, 5;
-    %load/vec4 v00000229accd6a10_0;
-    %addi 1, 0, 16;
-    %assign/vec4 v00000229accd6a10_0, 0;
-    %jmp T_3.8;
-T_3.7 ;
-    %pushi/vec4 0, 0, 16;
-    %assign/vec4 v00000229accd6a10_0, 0;
-    %pushi/vec4 2, 0, 2;
-    %assign/vec4 v00000229acd79290_0, 0;
-T_3.8 ;
-    %jmp T_3.4;
-T_3.2 ;
-    %load/vec4 v00000229accd6a10_0;
-    %pad/u 32;
-    %cmpi/u 233, 0, 32;
-    %jmp/0xz  T_3.9, 5;
-    %load/vec4 v00000229accd6a10_0;
-    %addi 1, 0, 16;
-    %assign/vec4 v00000229accd6a10_0, 0;
-    %jmp T_3.10;
-T_3.9 ;
-    %pushi/vec4 0, 0, 16;
-    %assign/vec4 v00000229accd6a10_0, 0;
-    %load/vec4 v00000229acd79dd0_0;
-    %ix/load 5, 0, 0;
-    %ix/getv 4, v00000229acd00f00_0;
-    %assign/vec4/off/d v00000229acd798d0_0, 4, 5;
-    %load/vec4 v00000229acd00f00_0;
-    %addi 1, 0, 4;
-    %assign/vec4 v00000229acd00f00_0, 0;
-    %load/vec4 v00000229acd00f00_0;
-    %pad/u 32;
-    %cmpi/e 7, 0, 32;
-    %jmp/0xz  T_3.11, 4;
-    %pushi/vec4 3, 0, 2;
-    %assign/vec4 v00000229acd79290_0, 0;
-T_3.11 ;
-T_3.10 ;
-    %jmp T_3.4;
-T_3.3 ;
-    %load/vec4 v00000229accd6a10_0;
-    %pad/u 32;
-    %cmpi/u 233, 0, 32;
-    %jmp/0xz  T_3.13, 5;
-    %load/vec4 v00000229accd6a10_0;
-    %addi 1, 0, 16;
-    %assign/vec4 v00000229accd6a10_0, 0;
-    %jmp T_3.14;
-T_3.13 ;
-    %pushi/vec4 0, 0, 2;
-    %assign/vec4 v00000229acd79290_0, 0;
-    %load/vec4 v00000229acd798d0_0;
-    %assign/vec4 v00000229acd0de70_0, 0;
-    %pushi/vec4 1, 0, 1;
-    %assign/vec4 v00000229acd79470_0, 0;
-    %pushi/vec4 1, 0, 1;
-    %assign/vec4 v00000229acd0df10_0, 0;
-T_3.14 ;
-    %jmp T_3.4;
-T_3.4 ;
-    %pop/vec4 1;
-    %jmp T_3;
-    .thread T_3;
-    .scope S_00000229acd190a0;
-T_4 ;
-    %pushi/vec4 0, 0, 1;
-    %store/vec4 v00000229acd79b50_0, 0, 1;
-    %pushi/vec4 0, 0, 1;
-    %store/vec4 v00000229acd79150_0, 0, 1;
-    %pushi/vec4 0, 0, 8;
-    %store/vec4 v00000229acd790b0_0, 0, 8;
-    %end;
-    .thread T_4;
-    .scope S_00000229acd190a0;
-T_5 ;
-    %delay 10000, 0;
-    %load/vec4 v00000229acd79b50_0;
-    %inv;
-    %store/vec4 v00000229acd79b50_0, 0, 1;
-    %jmp T_5;
-    .thread T_5;
-    .scope S_00000229acd190a0;
-T_6 ;
-    %vpi_call 2 39 "$display", "D\303\251but de la simulation" {0 0 0};
-    %vpi_call 2 40 "$dumpfile", "uart_loopback.vcd" {0 0 0};
-    %vpi_call 2 41 "$dumpvars", 32'sb00000000000000000000000000000000, S_00000229acd190a0 {0 0 0};
-    %delay 200000, 0;
-    %pushi/vec4 165, 0, 8;
-    %store/vec4 v00000229acd790b0_0, 0, 8;
-    %pushi/vec4 1, 0, 1;
-    %store/vec4 v00000229acd79150_0, 0, 1;
-    %delay 20000, 0;
-    %pushi/vec4 0, 0, 1;
-    %store/vec4 v00000229acd79150_0, 0, 1;
-T_6.0 ;
-    %load/vec4 v00000229acd7bd80_0;
-    %pad/u 32;
-    %pushi/vec4 1, 0, 32;
-    %cmp/e;
-    %flag_get/vec4 4;
-    %cmpi/ne 1, 0, 1;
-    %jmp/0xz T_6.1, 6;
-    %wait E_00000229accfc720;
-    %jmp T_6.0;
-T_6.1 ;
-    %vpi_call 2 56 "$display", "Data envoyee : 0x%h", v00000229acd790b0_0 {0 0 0};
-    %vpi_call 2 57 "$display", "Data recue   : 0x%h", v00000229acd79bf0_0 {0 0 0};
-    %load/vec4 v00000229acd79bf0_0;
-    %load/vec4 v00000229acd790b0_0;
-    %cmp/e;
-    %jmp/0xz  T_6.2, 4;
-    %vpi_call 2 60 "$display", "Test reussi !" {0 0 0};
-    %jmp T_6.3;
-T_6.2 ;
-    %vpi_call 2 62 "$display", "Test echoue..." {0 0 0};
-T_6.3 ;
-    %delay 200000, 0;
-    %vpi_call 2 66 "$finish" {0 0 0};
-    %end;
-    .thread T_6;
-# The file index is used to find the file name in the following table.
-:file_names 6;
-    "N/A";
-    "<interactive>";
-    "tb_top_uart_rx_tx.v";
-    "top_uart_rx_tx.v";
-    "uart_rx.v";
-    "uart_tx.v";

Semaine 1/UART/uart_rx.v

@@ -35,11 +35,11 @@ module uart_rx (
                 end
     
                 START: begin
-                    if (clk_count < (BIT_PERIOD + (BIT_PERIOD / 2)) - 1) begin
+                    if (clk_count < (BIT_PERIOD / 2) - 1) begin  // Attendre juste 0.5 bit
-                        clk_count <= clk_count + 1; 
+                        clk_count <= clk_count + 1;
                     end else begin
-                        clk_count <= 0; 
+                        clk_count <= 0;
-                        state <= DATA;  // Passer à l'état de réception des données après le start bit
+                        state <= DATA;
                     end
                 end
 
@@ -50,7 +50,7 @@ module uart_rx (
                         clk_count <= 0; 
                         rx_data[bit_index] <= rx; // Recevoir les données (8 bits)
                         bit_index <= bit_index + 1; 
-
+                        
                         if (bit_index == 7) begin
                             state <= STOP; // Passer à l'état d'arrêt
                         end
@@ -62,7 +62,7 @@ module uart_rx (
                         clk_count <= clk_count + 1; 
                     end else begin
                         state <= IDLE; 
-                        data <= rx_data; 
+                        data <= rx_data;
                         valid <= 1; 
                         ready <= 1; 
                     end

Semaine 1/UART/uart_rx_tb

@@ -1,256 +0,0 @@
-#! 
-:ivl_version "13.0 (devel)" "(s20250103-31-g7e238e7ca-dirty)";
-:ivl_delay_selection "TYPICAL";
-:vpi_time_precision - 12;
-:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\system.vpi";
-:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\vhdl_sys.vpi";
-:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\vhdl_textio.vpi";
-:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\v2005_math.vpi";
-:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\va_math.vpi";
-S_000001de0ef7b970 .scope module, "tb_uart_rx" "tb_uart_rx" 2 3;
- .timescale -9 -12;
-P_000001de0f08dd40 .param/l "BAUD_RATE" 1 2 12, +C4<00000000000000011100001000000000>;
-P_000001de0f08dd78 .param/l "BIT_PERIOD" 1 2 13, +C4<00000000000000000000000011101010>;
-P_000001de0f08ddb0 .param/l "CLK_FREQ" 1 2 11, +C4<00000001100110111111110011000000>;
-P_000001de0f08dde8 .param/l "CLK_PERIOD_NS" 1 2 14, +C4<00000000000000000000000000100101>;
-v000001de0f0f5ab0_0 .var "clk", 0 0;
-v000001de0f0f6190_0 .net "data", 7 0, v000001de0f066a10_0;  1 drivers
-v000001de0f0f6230_0 .var/i "i", 31 0;
-v000001de0f0f62d0_0 .net "ready", 0 0, v000001de0f08f950_0;  1 drivers
-v000001de0f0f6410_0 .var "rx", 0 0;
-v000001de0f0f5fb0_0 .net "valid", 0 0, v000001de0f0f60f0_0;  1 drivers
-S_000001de0f08f630 .scope module, "rx_instance" "uart_rx" 2 19, 3 1 0, S_000001de0ef7b970;
- .timescale 0 0;
-    .port_info 0 /INPUT 1 "clk";
-    .port_info 1 /INPUT 1 "rx";
-    .port_info 2 /OUTPUT 8 "data";
-    .port_info 3 /OUTPUT 1 "valid";
-    .port_info 4 /OUTPUT 1 "ready";
-P_000001de0f08f7c0 .param/l "BAUD_RATE" 0 3 10, +C4<00000000000000011100001000000000>;
-P_000001de0f08f7f8 .param/l "BIT_PERIOD" 1 3 12, +C4<00000000000000000000000011101010>;
-P_000001de0f08f830 .param/l "CLK_FREQ" 0 3 9, +C4<00000001100110111111110011000000>;
-P_000001de0f08f868 .param/l "DATA" 1 3 16, C4<10>;
-P_000001de0f08f8a0 .param/l "IDLE" 1 3 14, C4<00>;
-P_000001de0f08f8d8 .param/l "START" 1 3 15, C4<01>;
-P_000001de0f08f910 .param/l "STOP" 1 3 17, C4<11>;
-v000001de0f066e60_0 .var "bit_index", 3 0;
-v000001de0ef7bb00_0 .net "clk", 0 0, v000001de0f0f5ab0_0;  1 drivers
-v000001de0ef7bf20_0 .var "clk_count", 15 0;
-v000001de0f066a10_0 .var "data", 7 0;
-v000001de0f08f950_0 .var "ready", 0 0;
-v000001de0f08f9f0_0 .net "rx", 0 0, v000001de0f0f6410_0;  1 drivers
-v000001de0f08de30_0 .var "rx_data", 7 0;
-v000001de0f0f5d30_0 .var "state", 1 0;
-v000001de0f0f60f0_0 .var "valid", 0 0;
-E_000001de0f08e270 .event posedge, v000001de0ef7bb00_0;
-S_000001de0f0a0300 .scope task, "send_bit" "send_bit" 2 29, 2 29 0, S_000001de0ef7b970;
- .timescale -9 -12;
-v000001de0f0f5a10_0 .var "b", 0 0;
-TD_tb_uart_rx.send_bit ;
-    %load/vec4 v000001de0f0f5a10_0;
-    %assign/vec4 v000001de0f0f6410_0, 0;
-    %delay 8658000, 0;
-    %end;
-S_000001de0f0a0490 .scope task, "send_byte" "send_byte" 2 38, 2 38 0, S_000001de0ef7b970;
- .timescale -9 -12;
-v000001de0f0f6370_0 .var "byte", 7 0;
-TD_tb_uart_rx.send_byte ;
-    %pushi/vec4 0, 0, 1;
-    %store/vec4 v000001de0f0f5a10_0, 0, 1;
-    %fork TD_tb_uart_rx.send_bit, S_000001de0f0a0300;
-    %join;
-    %pushi/vec4 0, 0, 32;
-    %store/vec4 v000001de0f0f6230_0, 0, 32;
-T_1.0 ; Top of for-loop
-    %load/vec4 v000001de0f0f6230_0;
-    %cmpi/s 8, 0, 32;
-	  %jmp/0xz T_1.1, 5;
-    %load/vec4 v000001de0f0f6370_0;
-    %load/vec4 v000001de0f0f6230_0;
-    %part/s 1;
-    %store/vec4 v000001de0f0f5a10_0, 0, 1;
-    %fork TD_tb_uart_rx.send_bit, S_000001de0f0a0300;
-    %join;
-T_1.2 ; for-loop step statement
-    %load/vec4 v000001de0f0f6230_0;
-    %addi 1, 0, 32;
-    %store/vec4 v000001de0f0f6230_0, 0, 32;
-    %jmp T_1.0;
-T_1.1 ; for-loop exit label
-    %pushi/vec4 1, 0, 1;
-    %store/vec4 v000001de0f0f5a10_0, 0, 1;
-    %fork TD_tb_uart_rx.send_bit, S_000001de0f0a0300;
-    %join;
-    %delay 8658000, 0;
-    %end;
-    .scope S_000001de0f08f630;
-T_2 ;
-    %pushi/vec4 0, 0, 1;
-    %store/vec4 v000001de0f0f60f0_0, 0, 1;
-    %pushi/vec4 1, 0, 1;
-    %store/vec4 v000001de0f08f950_0, 0, 1;
-    %pushi/vec4 0, 0, 2;
-    %store/vec4 v000001de0f0f5d30_0, 0, 2;
-    %pushi/vec4 0, 0, 8;
-    %store/vec4 v000001de0f08de30_0, 0, 8;
-    %end;
-    .thread T_2;
-    .scope S_000001de0f08f630;
-T_3 ;
-    %wait E_000001de0f08e270;
-    %load/vec4 v000001de0f0f5d30_0;
-    %dup/vec4;
-    %pushi/vec4 0, 0, 2;
-    %cmp/u;
-    %jmp/1 T_3.0, 6;
-    %dup/vec4;
-    %pushi/vec4 1, 0, 2;
-    %cmp/u;
-    %jmp/1 T_3.1, 6;
-    %dup/vec4;
-    %pushi/vec4 2, 0, 2;
-    %cmp/u;
-    %jmp/1 T_3.2, 6;
-    %dup/vec4;
-    %pushi/vec4 3, 0, 2;
-    %cmp/u;
-    %jmp/1 T_3.3, 6;
-    %jmp T_3.4;
-T_3.0 ;
-    %pushi/vec4 1, 0, 1;
-    %assign/vec4 v000001de0f08f950_0, 0;
-    %load/vec4 v000001de0f08f9f0_0;
-    %nor/r;
-    %flag_set/vec4 8;
-    %jmp/0xz  T_3.5, 8;
-    %pushi/vec4 1, 0, 2;
-    %assign/vec4 v000001de0f0f5d30_0, 0;
-    %pushi/vec4 0, 0, 16;
-    %assign/vec4 v000001de0ef7bf20_0, 0;
-    %pushi/vec4 0, 0, 4;
-    %assign/vec4 v000001de0f066e60_0, 0;
-    %pushi/vec4 0, 0, 1;
-    %assign/vec4 v000001de0f0f60f0_0, 0;
-    %pushi/vec4 0, 0, 1;
-    %assign/vec4 v000001de0f08f950_0, 0;
-T_3.5 ;
-    %jmp T_3.4;
-T_3.1 ;
-    %load/vec4 v000001de0ef7bf20_0;
-    %pad/u 32;
-    %cmpi/u 116, 0, 32;
-    %jmp/0xz  T_3.7, 5;
-    %load/vec4 v000001de0ef7bf20_0;
-    %addi 1, 0, 16;
-    %assign/vec4 v000001de0ef7bf20_0, 0;
-    %jmp T_3.8;
-T_3.7 ;
-    %pushi/vec4 0, 0, 16;
-    %assign/vec4 v000001de0ef7bf20_0, 0;
-    %pushi/vec4 2, 0, 2;
-    %assign/vec4 v000001de0f0f5d30_0, 0;
-T_3.8 ;
-    %jmp T_3.4;
-T_3.2 ;
-    %load/vec4 v000001de0ef7bf20_0;
-    %pad/u 32;
-    %cmpi/u 233, 0, 32;
-    %jmp/0xz  T_3.9, 5;
-    %load/vec4 v000001de0ef7bf20_0;
-    %addi 1, 0, 16;
-    %assign/vec4 v000001de0ef7bf20_0, 0;
-    %jmp T_3.10;
-T_3.9 ;
-    %pushi/vec4 0, 0, 16;
-    %assign/vec4 v000001de0ef7bf20_0, 0;
-    %load/vec4 v000001de0f08f9f0_0;
-    %ix/load 5, 0, 0;
-    %ix/getv 4, v000001de0f066e60_0;
-    %assign/vec4/off/d v000001de0f08de30_0, 4, 5;
-    %load/vec4 v000001de0f066e60_0;
-    %addi 1, 0, 4;
-    %assign/vec4 v000001de0f066e60_0, 0;
-    %load/vec4 v000001de0f066e60_0;
-    %pad/u 32;
-    %cmpi/e 7, 0, 32;
-    %jmp/0xz  T_3.11, 4;
-    %pushi/vec4 3, 0, 2;
-    %assign/vec4 v000001de0f0f5d30_0, 0;
-T_3.11 ;
-T_3.10 ;
-    %jmp T_3.4;
-T_3.3 ;
-    %load/vec4 v000001de0ef7bf20_0;
-    %pad/u 32;
-    %cmpi/u 233, 0, 32;
-    %jmp/0xz  T_3.13, 5;
-    %load/vec4 v000001de0ef7bf20_0;
-    %addi 1, 0, 16;
-    %assign/vec4 v000001de0ef7bf20_0, 0;
-    %jmp T_3.14;
-T_3.13 ;
-    %pushi/vec4 0, 0, 2;
-    %assign/vec4 v000001de0f0f5d30_0, 0;
-    %load/vec4 v000001de0f08de30_0;
-    %assign/vec4 v000001de0f066a10_0, 0;
-    %pushi/vec4 1, 0, 1;
-    %assign/vec4 v000001de0f0f60f0_0, 0;
-    %pushi/vec4 1, 0, 1;
-    %assign/vec4 v000001de0f08f950_0, 0;
-T_3.14 ;
-    %jmp T_3.4;
-T_3.4 ;
-    %pop/vec4 1;
-    %jmp T_3;
-    .thread T_3;
-    .scope S_000001de0ef7b970;
-T_4 ;
-    %pushi/vec4 0, 0, 1;
-    %store/vec4 v000001de0f0f5ab0_0, 0, 1;
-    %pushi/vec4 1, 0, 1;
-    %store/vec4 v000001de0f0f6410_0, 0, 1;
-    %end;
-    .thread T_4;
-    .scope S_000001de0ef7b970;
-T_5 ;
-    %delay 18000, 0;
-    %load/vec4 v000001de0f0f5ab0_0;
-    %inv;
-    %store/vec4 v000001de0f0f5ab0_0, 0, 1;
-    %jmp T_5;
-    .thread T_5;
-    .scope S_000001de0ef7b970;
-T_6 ;
-    %vpi_call 2 50 "$display", "Start UART RX test" {0 0 0};
-    %delay 100000, 0;
-    %pushi/vec4 85, 0, 8;
-    %store/vec4 v000001de0f0f6370_0, 0, 8;
-    %fork TD_tb_uart_rx.send_byte, S_000001de0f0a0490;
-    %join;
-    %delay 86580000, 0;
-    %load/vec4 v000001de0f0f5fb0_0;
-    %flag_set/vec4 9;
-    %flag_get/vec4 9;
-    %jmp/0 T_6.2, 9;
-    %load/vec4 v000001de0f0f6190_0;
-    %pushi/vec4 85, 0, 8;
-    %cmp/e;
-    %flag_get/vec4 4;
-    %and;
-T_6.2;
-    %flag_set/vec4 8;
-    %jmp/0xz  T_6.0, 8;
-    %vpi_call 2 58 "$display", "Test ok : data = %b", v000001de0f0f6190_0 {0 0 0};
-    %jmp T_6.1;
-T_6.0 ;
-    %vpi_call 2 60 "$display", "Test pas ok : data = %b, valid = %b", v000001de0f0f6190_0, v000001de0f0f5fb0_0 {0 0 0};
-T_6.1 ;
-    %vpi_call 2 62 "$finish" {0 0 0};
-    %end;
-    .thread T_6;
-# The file index is used to find the file name in the following table.
-:file_names 4;
-    "N/A";
-    "<interactive>";
-    "tb_uart_rx.v";
-    "uart_rx.v";

Semaine 1/UART/uart_tx.v

@@ -24,10 +24,9 @@ module uart_tx(
     always @(posedge clk) begin
         case(state)
             IDLE: begin
-                busy <= 0;
                 tx <= 1; 
 
-                if (start && !busy) begin
+                if (start) begin
                     tx_data <= data;
                     bit_index <= 0;
                     clk_count <= 0;

Semaine 1/UART/uart_tx_tb

@@ -1,247 +0,0 @@
-#! 
-:ivl_version "13.0 (devel)" "(s20250103-31-g7e238e7ca-dirty)";
-:ivl_delay_selection "TYPICAL";
-:vpi_time_precision - 12;
-:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\system.vpi";
-:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\vhdl_sys.vpi";
-:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\vhdl_textio.vpi";
-:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\v2005_math.vpi";
-:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\va_math.vpi";
-S_00000232894a6720 .scope module, "tb_uart_tx" "tb_uart_tx" 2 3;
- .timescale -9 -12;
-v00000232894d6a90_0 .net "busy", 0 0, v00000232894cb650_0;  1 drivers
-v00000232894d6b30_0 .var "clk", 0 0;
-v00000232894d73a0_0 .var "data", 7 0;
-v00000232894d7b20_0 .var "start", 0 0;
-v00000232894d6e00_0 .net "tx", 0 0, v00000232894e06e0_0;  1 drivers
-E_00000232894caed0 .event anyedge, v00000232894cb650_0;
-S_00000232894a68b0 .scope module, "tx_instance" "uart_tx" 2 16, 3 1 0, S_00000232894a6720;
- .timescale 0 0;
-    .port_info 0 /INPUT 1 "clk";
-    .port_info 1 /INPUT 1 "start";
-    .port_info 2 /INPUT 8 "data";
-    .port_info 3 /OUTPUT 1 "tx";
-    .port_info 4 /OUTPUT 1 "busy";
-P_00000232894e02d0 .param/l "BAUD_RATE" 0 3 10, +C4<00000000000000011100001000000000>;
-P_00000232894e0308 .param/l "BIT_PERIOD" 1 3 11, +C4<00000000000000000000000011101010>;
-P_00000232894e0340 .param/l "CLK_FREQ" 0 3 9, +C4<00000001100110111111110011000000>;
-P_00000232894e0378 .param/l "DATA" 1 3 15, C4<10>;
-P_00000232894e03b0 .param/l "IDLE" 1 3 13, C4<00>;
-P_00000232894e03e8 .param/l "START" 1 3 14, C4<01>;
-P_00000232894e0420 .param/l "STOP" 1 3 16, C4<11>;
-v00000232894a6a40_0 .var "bit_index", 3 0;
-v00000232894cb650_0 .var "busy", 0 0;
-v00000232894a6e60_0 .net "clk", 0 0, v00000232894d6b30_0;  1 drivers
-v00000232894e0460_0 .var "clk_count", 15 0;
-v00000232894e0500_0 .net "data", 7 0, v00000232894d73a0_0;  1 drivers
-v00000232894e05a0_0 .net "start", 0 0, v00000232894d7b20_0;  1 drivers
-v00000232894e0640_0 .var "state", 1 0;
-v00000232894e06e0_0 .var "tx", 0 0;
-v00000232894d69f0_0 .var "tx_data", 7 0;
-E_00000232894caf50 .event posedge, v00000232894a6e60_0;
-    .scope S_00000232894a68b0;
-T_0 ;
-    %pushi/vec4 1, 0, 1;
-    %store/vec4 v00000232894e06e0_0, 0, 1;
-    %pushi/vec4 0, 0, 1;
-    %store/vec4 v00000232894cb650_0, 0, 1;
-    %pushi/vec4 0, 0, 2;
-    %store/vec4 v00000232894e0640_0, 0, 2;
-    %pushi/vec4 0, 0, 4;
-    %store/vec4 v00000232894a6a40_0, 0, 4;
-    %pushi/vec4 0, 0, 16;
-    %store/vec4 v00000232894e0460_0, 0, 16;
-    %pushi/vec4 0, 0, 8;
-    %store/vec4 v00000232894d69f0_0, 0, 8;
-    %end;
-    .thread T_0;
-    .scope S_00000232894a68b0;
-T_1 ;
-    %wait E_00000232894caf50;
-    %load/vec4 v00000232894e0640_0;
-    %dup/vec4;
-    %pushi/vec4 0, 0, 2;
-    %cmp/u;
-    %jmp/1 T_1.0, 6;
-    %dup/vec4;
-    %pushi/vec4 1, 0, 2;
-    %cmp/u;
-    %jmp/1 T_1.1, 6;
-    %dup/vec4;
-    %pushi/vec4 2, 0, 2;
-    %cmp/u;
-    %jmp/1 T_1.2, 6;
-    %dup/vec4;
-    %pushi/vec4 3, 0, 2;
-    %cmp/u;
-    %jmp/1 T_1.3, 6;
-    %jmp T_1.4;
-T_1.0 ;
-    %pushi/vec4 0, 0, 1;
-    %assign/vec4 v00000232894cb650_0, 0;
-    %pushi/vec4 1, 0, 1;
-    %assign/vec4 v00000232894e06e0_0, 0;
-    %load/vec4 v00000232894e05a0_0;
-    %flag_set/vec4 9;
-    %flag_get/vec4 9;
-    %jmp/0 T_1.7, 9;
-    %load/vec4 v00000232894cb650_0;
-    %nor/r;
-    %and;
-T_1.7;
-    %flag_set/vec4 8;
-    %jmp/0xz  T_1.5, 8;
-    %load/vec4 v00000232894e0500_0;
-    %assign/vec4 v00000232894d69f0_0, 0;
-    %pushi/vec4 0, 0, 4;
-    %assign/vec4 v00000232894a6a40_0, 0;
-    %pushi/vec4 0, 0, 16;
-    %assign/vec4 v00000232894e0460_0, 0;
-    %pushi/vec4 1, 0, 1;
-    %assign/vec4 v00000232894cb650_0, 0;
-    %pushi/vec4 1, 0, 2;
-    %assign/vec4 v00000232894e0640_0, 0;
-T_1.5 ;
-    %jmp T_1.4;
-T_1.1 ;
-    %load/vec4 v00000232894e0460_0;
-    %pad/u 32;
-    %cmpi/u 233, 0, 32;
-    %jmp/0xz  T_1.8, 5;
-    %load/vec4 v00000232894e0460_0;
-    %addi 1, 0, 16;
-    %assign/vec4 v00000232894e0460_0, 0;
-    %pushi/vec4 0, 0, 1;
-    %assign/vec4 v00000232894e06e0_0, 0;
-    %jmp T_1.9;
-T_1.8 ;
-    %pushi/vec4 2, 0, 2;
-    %assign/vec4 v00000232894e0640_0, 0;
-    %pushi/vec4 0, 0, 16;
-    %assign/vec4 v00000232894e0460_0, 0;
-T_1.9 ;
-    %jmp T_1.4;
-T_1.2 ;
-    %load/vec4 v00000232894e0460_0;
-    %pad/u 32;
-    %cmpi/u 233, 0, 32;
-    %jmp/0xz  T_1.10, 5;
-    %load/vec4 v00000232894e0460_0;
-    %addi 1, 0, 16;
-    %assign/vec4 v00000232894e0460_0, 0;
-    %jmp T_1.11;
-T_1.10 ;
-    %load/vec4 v00000232894a6a40_0;
-    %pad/u 32;
-    %cmpi/u 8, 0, 32;
-    %jmp/0xz  T_1.12, 5;
-    %load/vec4 v00000232894d69f0_0;
-    %load/vec4 v00000232894a6a40_0;
-    %part/u 1;
-    %assign/vec4 v00000232894e06e0_0, 0;
-    %load/vec4 v00000232894a6a40_0;
-    %addi 1, 0, 4;
-    %assign/vec4 v00000232894a6a40_0, 0;
-    %pushi/vec4 0, 0, 16;
-    %assign/vec4 v00000232894e0460_0, 0;
-    %jmp T_1.13;
-T_1.12 ;
-    %pushi/vec4 3, 0, 2;
-    %assign/vec4 v00000232894e0640_0, 0;
-T_1.13 ;
-T_1.11 ;
-    %jmp T_1.4;
-T_1.3 ;
-    %pushi/vec4 1, 0, 1;
-    %assign/vec4 v00000232894e06e0_0, 0;
-    %load/vec4 v00000232894e0460_0;
-    %pad/u 32;
-    %cmpi/u 233, 0, 32;
-    %jmp/0xz  T_1.14, 5;
-    %load/vec4 v00000232894e0460_0;
-    %addi 1, 0, 16;
-    %assign/vec4 v00000232894e0460_0, 0;
-    %jmp T_1.15;
-T_1.14 ;
-    %pushi/vec4 0, 0, 16;
-    %assign/vec4 v00000232894e0460_0, 0;
-    %pushi/vec4 0, 0, 1;
-    %assign/vec4 v00000232894cb650_0, 0;
-    %pushi/vec4 0, 0, 2;
-    %assign/vec4 v00000232894e0640_0, 0;
-T_1.15 ;
-    %jmp T_1.4;
-T_1.4 ;
-    %pop/vec4 1;
-    %jmp T_1;
-    .thread T_1;
-    .scope S_00000232894a6720;
-T_2 ;
-    %pushi/vec4 0, 0, 1;
-    %store/vec4 v00000232894d6b30_0, 0, 1;
-    %pushi/vec4 0, 0, 1;
-    %store/vec4 v00000232894d7b20_0, 0, 1;
-    %pushi/vec4 0, 0, 8;
-    %store/vec4 v00000232894d73a0_0, 0, 8;
-    %end;
-    .thread T_2;
-    .scope S_00000232894a6720;
-T_3 ;
-    %delay 18500, 0;
-    %load/vec4 v00000232894d6b30_0;
-    %inv;
-    %store/vec4 v00000232894d6b30_0, 0, 1;
-    %jmp T_3;
-    .thread T_3;
-    .scope S_00000232894a6720;
-T_4 ;
-    %vpi_call 2 25 "$dumpfile", "uart_tx.vcd" {0 0 0};
-    %vpi_call 2 26 "$dumpvars", 32'sb00000000000000000000000000000000, S_00000232894a6720 {0 0 0};
-    %delay 100000, 0;
-    %pushi/vec4 165, 0, 8;
-    %assign/vec4 v00000232894d73a0_0, 0;
-    %pushi/vec4 1, 0, 1;
-    %assign/vec4 v00000232894d7b20_0, 0;
-    %delay 37000, 0;
-    %pushi/vec4 0, 0, 1;
-    %assign/vec4 v00000232894d7b20_0, 0;
-T_4.0 ;
-    %load/vec4 v00000232894d6a90_0;
-    %pad/u 32;
-    %pushi/vec4 0, 0, 32;
-    %cmp/e;
-    %flag_get/vec4 4;
-    %cmpi/ne 1, 0, 1;
-    %jmp/0xz T_4.1, 6;
-    %wait E_00000232894caed0;
-    %jmp T_4.0;
-T_4.1 ;
-    %delay 1000000, 0;
-    %pushi/vec4 60, 0, 8;
-    %assign/vec4 v00000232894d73a0_0, 0;
-    %pushi/vec4 1, 0, 1;
-    %assign/vec4 v00000232894d7b20_0, 0;
-    %delay 37000, 0;
-    %pushi/vec4 0, 0, 1;
-    %assign/vec4 v00000232894d7b20_0, 0;
-T_4.2 ;
-    %load/vec4 v00000232894d6a90_0;
-    %pad/u 32;
-    %pushi/vec4 0, 0, 32;
-    %cmp/e;
-    %flag_get/vec4 4;
-    %cmpi/ne 1, 0, 1;
-    %jmp/0xz T_4.3, 6;
-    %wait E_00000232894caed0;
-    %jmp T_4.2;
-T_4.3 ;
-    %delay 1000000, 0;
-    %vpi_call 2 46 "$stop" {0 0 0};
-    %end;
-    .thread T_4;
-# The file index is used to find the file name in the following table.
-:file_names 4;
-    "N/A";
-    "<interactive>";
-    "tb_uart_tx.v";
-    "uart_tx.v";

Semaine 1/UART/uart_tx_tb_old

@@ -1,204 +0,0 @@
-#! 
-:ivl_version "13.0 (devel)" "(s20250103-31-g7e238e7ca-dirty)";
-:ivl_delay_selection "TYPICAL";
-:vpi_time_precision - 12;
-:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\system.vpi";
-:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\vhdl_sys.vpi";
-:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\vhdl_textio.vpi";
-:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\v2005_math.vpi";
-:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\va_math.vpi";
-S_00000175b6316720 .scope module, "tb_uart_tx" "tb_uart_tx" 2 3;
- .timescale -9 -12;
-v00000175b5febe70_0 .net "busy", 0 0, v00000175b5feb060_0;  1 drivers
-v00000175b5febf10_0 .var "clk", 0 0;
-v00000175b639b030_0 .var "data", 7 0;
-v00000175b63466a0_0 .var "start", 0 0;
-v00000175b6346a60_0 .net "tx", 0 0, v00000175b5febd30_0;  1 drivers
-E_00000175b5fead00 .event anyedge, v00000175b5feb060_0;
-S_00000175b63168b0 .scope module, "tx_instance" "uart_tx" 2 16, 3 1 0, S_00000175b6316720;
- .timescale 0 0;
-    .port_info 0 /INPUT 1 "clk";
-    .port_info 1 /INPUT 1 "start";
-    .port_info 2 /INPUT 8 "data";
-    .port_info 3 /OUTPUT 1 "tx";
-    .port_info 4 /OUTPUT 1 "busy";
-P_00000175b634db00 .param/l "BAUD_RATE" 0 3 10, +C4<00000000000000011100001000000000>;
-P_00000175b634db38 .param/l "BIT_PERIOD" 1 3 12, +C4<00000000000000000000000011101010>;
-P_00000175b634db70 .param/l "CLK_FREQ" 0 3 9, +C4<00000001100110111111110011000000>;
-v00000175b6316a40_0 .var "bit_index", 3 0;
-v00000175b5feb060_0 .var "busy", 0 0;
-v00000175b6316e60_0 .net "clk", 0 0, v00000175b5febf10_0;  1 drivers
-v00000175b5febb50_0 .var "clk_count", 15 0;
-v00000175b5febbf0_0 .net "data", 7 0, v00000175b639b030_0;  1 drivers
-v00000175b5febc90_0 .net "start", 0 0, v00000175b63466a0_0;  1 drivers
-v00000175b5febd30_0 .var "tx", 0 0;
-v00000175b5febdd0_0 .var "tx_data", 7 0;
-E_00000175b5fea980 .event posedge, v00000175b6316e60_0;
-    .scope S_00000175b63168b0;
-T_0 ;
-    %pushi/vec4 0, 0, 8;
-    %store/vec4 v00000175b5febdd0_0, 0, 8;
-    %end;
-    .thread T_0;
-    .scope S_00000175b63168b0;
-T_1 ;
-    %pushi/vec4 1, 0, 1;
-    %store/vec4 v00000175b5febd30_0, 0, 1;
-    %pushi/vec4 0, 0, 1;
-    %store/vec4 v00000175b5feb060_0, 0, 1;
-    %end;
-    .thread T_1;
-    .scope S_00000175b63168b0;
-T_2 ;
-    %wait E_00000175b5fea980;
-    %load/vec4 v00000175b5febc90_0;
-    %flag_set/vec4 9;
-    %flag_get/vec4 9;
-    %jmp/0 T_2.2, 9;
-    %load/vec4 v00000175b5feb060_0;
-    %nor/r;
-    %and;
-T_2.2;
-    %flag_set/vec4 8;
-    %jmp/0xz  T_2.0, 8;
-    %pushi/vec4 1, 0, 1;
-    %assign/vec4 v00000175b5feb060_0, 0;
-    %pushi/vec4 0, 0, 4;
-    %assign/vec4 v00000175b6316a40_0, 0;
-    %pushi/vec4 0, 0, 16;
-    %assign/vec4 v00000175b5febb50_0, 0;
-    %load/vec4 v00000175b5febbf0_0;
-    %assign/vec4 v00000175b5febdd0_0, 0;
-    %pushi/vec4 1, 0, 1;
-    %assign/vec4 v00000175b5febd30_0, 0;
-    %jmp T_2.1;
-T_2.0 ;
-    %load/vec4 v00000175b5feb060_0;
-    %flag_set/vec4 8;
-    %jmp/0xz  T_2.3, 8;
-    %load/vec4 v00000175b5febb50_0;
-    %pad/u 32;
-    %cmpi/u 233, 0, 32;
-    %jmp/0xz  T_2.5, 5;
-    %load/vec4 v00000175b5febb50_0;
-    %addi 1, 0, 16;
-    %assign/vec4 v00000175b5febb50_0, 0;
-    %jmp T_2.6;
-T_2.5 ;
-    %pushi/vec4 0, 0, 16;
-    %assign/vec4 v00000175b5febb50_0, 0;
-    %load/vec4 v00000175b6316a40_0;
-    %pad/u 32;
-    %cmpi/e 0, 0, 32;
-    %jmp/0xz  T_2.7, 4;
-    %pushi/vec4 0, 0, 1;
-    %assign/vec4 v00000175b5febd30_0, 0;
-    %jmp T_2.8;
-T_2.7 ;
-    %load/vec4 v00000175b6316a40_0;
-    %pad/u 32;
-    %cmpi/u 9, 0, 32;
-    %jmp/0xz  T_2.9, 5;
-    %load/vec4 v00000175b5febdd0_0;
-    %load/vec4 v00000175b6316a40_0;
-    %pad/u 32;
-    %subi 1, 0, 32;
-    %part/u 1;
-    %assign/vec4 v00000175b5febd30_0, 0;
-    %jmp T_2.10;
-T_2.9 ;
-    %load/vec4 v00000175b6316a40_0;
-    %pad/u 32;
-    %cmpi/e 9, 0, 32;
-    %jmp/0xz  T_2.11, 4;
-    %pushi/vec4 1, 0, 1;
-    %assign/vec4 v00000175b5febd30_0, 0;
-    %jmp T_2.12;
-T_2.11 ;
-    %pushi/vec4 0, 0, 1;
-    %assign/vec4 v00000175b5feb060_0, 0;
-T_2.12 ;
-T_2.10 ;
-T_2.8 ;
-    %load/vec4 v00000175b6316a40_0;
-    %addi 1, 0, 4;
-    %assign/vec4 v00000175b6316a40_0, 0;
-T_2.6 ;
-    %jmp T_2.4;
-T_2.3 ;
-    %pushi/vec4 1, 0, 1;
-    %assign/vec4 v00000175b5febd30_0, 0;
-T_2.4 ;
-T_2.1 ;
-    %jmp T_2;
-    .thread T_2;
-    .scope S_00000175b6316720;
-T_3 ;
-    %pushi/vec4 0, 0, 1;
-    %store/vec4 v00000175b5febf10_0, 0, 1;
-    %pushi/vec4 0, 0, 1;
-    %store/vec4 v00000175b63466a0_0, 0, 1;
-    %pushi/vec4 0, 0, 8;
-    %store/vec4 v00000175b639b030_0, 0, 8;
-    %end;
-    .thread T_3;
-    .scope S_00000175b6316720;
-T_4 ;
-    %delay 18500, 0;
-    %load/vec4 v00000175b5febf10_0;
-    %inv;
-    %store/vec4 v00000175b5febf10_0, 0, 1;
-    %jmp T_4;
-    .thread T_4;
-    .scope S_00000175b6316720;
-T_5 ;
-    %vpi_call 2 25 "$dumpfile", "uart_tx.vcd" {0 0 0};
-    %vpi_call 2 26 "$dumpvars", 32'sb00000000000000000000000000000000, S_00000175b6316720 {0 0 0};
-    %delay 100000, 0;
-    %pushi/vec4 165, 0, 8;
-    %assign/vec4 v00000175b639b030_0, 0;
-    %pushi/vec4 1, 0, 1;
-    %assign/vec4 v00000175b63466a0_0, 0;
-    %delay 37000, 0;
-    %pushi/vec4 0, 0, 1;
-    %assign/vec4 v00000175b63466a0_0, 0;
-T_5.0 ;
-    %load/vec4 v00000175b5febe70_0;
-    %pad/u 32;
-    %pushi/vec4 0, 0, 32;
-    %cmp/e;
-    %flag_get/vec4 4;
-    %cmpi/ne 1, 0, 1;
-    %jmp/0xz T_5.1, 6;
-    %wait E_00000175b5fead00;
-    %jmp T_5.0;
-T_5.1 ;
-    %delay 1000000, 0;
-    %pushi/vec4 60, 0, 8;
-    %assign/vec4 v00000175b639b030_0, 0;
-    %pushi/vec4 1, 0, 1;
-    %assign/vec4 v00000175b63466a0_0, 0;
-    %delay 37000, 0;
-    %pushi/vec4 0, 0, 1;
-    %assign/vec4 v00000175b63466a0_0, 0;
-T_5.2 ;
-    %load/vec4 v00000175b5febe70_0;
-    %pad/u 32;
-    %pushi/vec4 0, 0, 32;
-    %cmp/e;
-    %flag_get/vec4 4;
-    %cmpi/ne 1, 0, 1;
-    %jmp/0xz T_5.3, 6;
-    %wait E_00000175b5fead00;
-    %jmp T_5.2;
-T_5.3 ;
-    %delay 1000000, 0;
-    %vpi_call 2 46 "$stop" {0 0 0};
-    %end;
-    .thread T_5;
-# The file index is used to find the file name in the following table.
-:file_names 4;
-    "N/A";
-    "<interactive>";
-    "tb_uart_tx.v";
-    "uart_tx_old.v";

Semaine 1/top_ultrason_uart.v

@@ -2,7 +2,7 @@ module top_ultrason_uart(
     input wire clk,
     input wire start,
     inout wire sig,
-    output wire tx,
+    output wire tx
 );
 
     parameter CLK_FREQ = 27_000_000;
@@ -41,15 +41,34 @@ module top_ultrason_uart(
         .tx(tx)
     );
 
-    always @(posedge clk) begin
+    reg [31:0] wait_counter;
-        if (state_sensor == 3'd6) begin // Lorsque la mesure est terminée, préparer les données
+    reg [1:0] state;
-            
+    localparam WAIT_NEXT_CYCLES = (CLK_FREQ / 1000) * 100; // 60 ms
-            tx_data <= distance;
-            tx_start <= 1;
 
-        end else begin
+    localparam START    = 2'd0;
-            tx_start <= 0;
+    localparam WAIT     = 2'd1;
-        end
+
+    always @(posedge clk) begin
+        case(state)
+            START:begin
+                if (state_sensor == 3'd6) begin // Lorsque la mesure est terminée, préparer les données
+            
+                    tx_data <= distance;
+                    tx_start <= 1;
+                    
+                    state <= WAIT;
+                end                   
+            end
+
+            WAIT:begin
+                tx_start <= 0;
+                wait_counter <= wait_counter + 1;
+                if (wait_counter >= WAIT_NEXT_CYCLES) begin
+                    state <= START;
+                    wait_counter <= 0;
+                end
+            end
+        endcase
     end
 
 endmodule