From 68000def79e902b25f0ee9626c33e64802128a3c Mon Sep 17 00:00:00 2001 From: Gamenight77 Date: Tue, 27 May 2025 10:31:52 +0200 Subject: [PATCH] Remove unnecessary blank line in dht11_interface module --- Semaine_7/DHT11_UART/IP/verilog/dht11_interface.v | 1 - 1 file changed, 1 deletion(-) diff --git a/Semaine_7/DHT11_UART/IP/verilog/dht11_interface.v b/Semaine_7/DHT11_UART/IP/verilog/dht11_interface.v index 8b6e6ea..379f4e8 100644 --- a/Semaine_7/DHT11_UART/IP/verilog/dht11_interface.v +++ b/Semaine_7/DHT11_UART/IP/verilog/dht11_interface.v @@ -34,7 +34,6 @@ module dht11_interface #( reg sig_in; assign io_dht11_sig = sig_dir ? sig_out : 1'bz; // Si sig_dir = 1, on force la valeur de sig_out sur la ligne, sinon on laisse la ligne libre (1'bz) - // === REGISTRES === reg [3:0] state;