From 6a5b90c8d128d73f67adab2442c1488c78f90944 Mon Sep 17 00:00:00 2001 From: Gamenight77 Date: Wed, 14 May 2025 10:31:48 +0200 Subject: [PATCH] Refactor DHT11 interface: change output wires to registers for data ready, busy, and error signals --- Semaine_5/DHT11/src/verilog/dht11_interface.v | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/Semaine_5/DHT11/src/verilog/dht11_interface.v b/Semaine_5/DHT11/src/verilog/dht11_interface.v index ec1116c..27753ad 100644 --- a/Semaine_5/DHT11/src/verilog/dht11_interface.v +++ b/Semaine_5/DHT11/src/verilog/dht11_interface.v @@ -2,11 +2,11 @@ module dht11_interface ( input wire i_clk, // 27 MHz inout wire io_dht11_sig, input wire i_start, - output wire o_dht11_data_ready, - output wire o_busy, + output reg o_dht11_data_ready, + output reg o_busy, output wire [7:0] o_temp_data, output wire [7:0] o_hum_data, - output wire o_dht11_error + output reg o_dht11_error ); // === DHT11 INTERFACE === @@ -169,7 +169,7 @@ module dht11_interface ( timer <= 0; bit_index <= bit_index + 1; - if (bit_index == 39) begin + if (bit_index == 39) begin // Code a testé ici pour etre sur de capter le dernier bit state <= DONE; end else begin state <= READ_BITS_LOW;