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forked from tanchou/Verilog

Fix path in build script and improve comments in testbench for ultrasonic commands

This commit is contained in:
Gamenight77
2025-05-16 17:06:57 +02:00
parent 933f38d071
commit 6ad0716f8f
2 changed files with 123 additions and 39 deletions

View File

@@ -2,7 +2,7 @@
setlocal
rem === Aller à la racine du projet ===
cd /d %~dp0\..
cd /d %~dp0\..\..
rem === Config de base ===
set DEVICE=GW2AR-LV18QN88C8/I7
@@ -19,7 +19,7 @@ if not exist runs (
)
echo === Étape 1 : Synthèse avec Yosys ===
yosys -p "read_verilog -sv src/verilog/%TOP%.v IP/verilog/ultrasonic_fpga.v IP/verilog/uart_tx_fifo.v IP/verilog/uart_rx_fifo.v IP/verilog/rxuartlite.v IP/verilog/fifo.v IP/verilog/uart_tx.v; synth_gowin -top %TOP% -json %JSON_FILE%"
yosys -p "read_verilog -sv src/verilog/%TOP%.v IP/verilog/ultrasonic_fpga.v IP/verilog/uart_tx_fifo.v IP/verilog/uart_rx_fifo.v IP/verilog/rxuartlite.v IP/verilog/txuartlite.v IP/verilog/fifo.v; synth_gowin -top %TOP% -json %JSON_FILE%"
if errorlevel 1 goto error
echo === Étape 2 : Placement & Routage avec nextpnr-himbaechel ===

View File

@@ -2,8 +2,9 @@
module tb_ultrason_commands;
// === Signaux ===
reg clk = 0;
always #18.5 clk = ~clk; // Génère une clock 27 MHz
always #18.5 clk = ~clk; // Horloge 27 MHz (période ~37ns)
wire tx, rx;
wire [5:0] leds;
@@ -14,14 +15,14 @@ module tb_ultrason_commands;
reg [7:0] data_in = 8'h00;
wire [7:0] data_out;
wire data_available;
reg rd_en = 0;
reg rd_en = 0; // Lecture FIFO
// === PARAMÈTRES ===
// === Paramètres ===
localparam CLK_FREQ = 27_000_000;
localparam BAUD_RATE = 115_200;
localparam CLK_PERIOD = 37; // ns
// === MODULE TESTÉ ===
// === Module testé ===
top_uart_ultrason_command dut (
.clk(clk),
.rx(rx),
@@ -30,10 +31,12 @@ module tb_ultrason_commands;
.leds(leds)
);
// === SIMULATION CAPTEUR ULTRASON ===
// === Simulation capteur ultrason ===
// Supposons que fake_sensor fournit un signal 'distance' pour vérification
wire [15:0] sensor_distance;
ultrasonic_sensor fake_sensor (
.clk(clk),
.signal(ultrason_sig)
.signal(ultrason_sig),
);
// === RX FIFO pour observer la sortie UART ===
@@ -42,13 +45,13 @@ module tb_ultrason_commands;
.BAUD_RATE(BAUD_RATE)
) uart_rx_fifo_inst (
.clk(clk),
.rx_pin(tx),
.rx_pin(tx),
.rd_en(rd_en),
.rd_data(data_out),
.data_available(data_available)
);
// === TX pour injecter une commande UART ===
// === TX pour injecter des commandes UART ===
uart_tx #(
.CLK_FREQ(CLK_FREQ),
.BAUD_RATE(BAUD_RATE)
@@ -61,43 +64,124 @@ module tb_ultrason_commands;
.rst_p(1'b0)
);
// === TEST SEQUENCE ===
// === Tâches pour simplifier les tests ===
task send_command(input [7:0] cmd);
begin
wait(tx_ready);
$display("[%0t ns] Envoi commande: %0d", $time, cmd);
data_in = cmd;
tx_enable = 1;
#(CLK_PERIOD * 2);
tx_enable = 0;
end
endtask
task read_distance(output [15:0] distance);
reg [7:0] lsb, msb;
begin
// Attendre premier octet (LSB)
wait(data_available);
#(CLK_PERIOD);
rd_en = 1;
#(CLK_PERIOD);
lsb = data_out;
rd_en = 0;
$display("[%0t ns] Reçu octet LSB: %0d", $time, lsb);
// Attendre second octet (MSB)
wait(data_available);
#(CLK_PERIOD);
rd_en = 1;
#(CLK_PERIOD);
msb = data_out;
rd_en = 0;
$display("[%0t ns] Reçu octet MSB: %0d", $time, msb);
distance = {msb, lsb};
end
endtask
task check_leds(input [7:0] cmd);
begin
#(CLK_PERIOD * 10); // Attendre mise à jour des LEDs
if (leds !== cmd[7:2]) begin
$display("[%0t ns] ERREUR: LEDs=%b, attendu=%b", $time, leds, cmd[7:2]);
end else begin
$display("[%0t ns] LEDs correctes: %b", $time, leds);
end
end
endtask
// === Séquence de test ===
initial begin
$dumpfile("runs/ultrason_commands.vcd");
$dumpvars(0, tb_ultrason_commands);
$display("==== Start UART Ultrasonic Test ====");
$display("==== Début Test UART Ultrason ====");
// Attendre que le TX soit prêt
wait(tx_ready);
$display(">> TX ready");
#100;
// Initialisation
#(CLK_PERIOD * 10);
// Envoyer la commande "ONE" (1)
data_in <= 8'd1;
tx_enable <= 1;
#20;
tx_enable <= 0;
$display(">> Command sent: %d", data_in);
// Lire 2 octets de réponse : LSB et MSB de la distance
repeat (2) begin
wait(data_available);
//D
#10; // Laisse le temps de valider le drapeau
rd_en <= 1; // Lecture de la FIFO
#30;
rd_en <= 0;
$display(">> Distance octet: %d", data_out);
#200;
// Test 1: Commande ONE (8'd1)
$display("=== Test 1: Commande ONE ===");
send_command(8'd1); // Commande: ONE
check_leds(8'd1);
begin
reg [15:0] received_distance;
read_distance(received_distance);
if (received_distance == sensor_distance) begin
$display("[%0t ns] Distance correcte: %0d", $time, received_distance);
end else begin
$display("[%0t ns] ERREUR: Distance reçue=%0d, attendu=%0d", $time, received_distance, sensor_distance);
end
end
$display("==== End UART Ultrasonic Test ====");
#10000;
// Test 2: Commande CONTINUOUS (8'd2)
$display("=== Test 2: Commande CONTINUOUS ===");
send_command(8'd2); // Commande: CONTINUOUS
check_leds(8'd2);
repeat (3) begin // Lire 3 mesures consécutives
reg [15:0] received_distance;
read_distance(received_distance);
if (received_distance == sensor_distance) begin
$display("[%0t ns] Distance continue correcte: %0d", $time, received_distance);
end else begin
$display("[%0t ns] ERREUR: Distance reçue=%0d, attendu=%0d", $time, received_distance, sensor_distance);
end
#(CLK_PERIOD * 13500000); // Attendre ~0.5s (délai dans WAIT)
end
// Test 3: Commande STOP (8'd3)
$display("=== Test 3: Commande STOP ===");
send_command(8'd3); // Commande: STOP
check_leds(8'd3);
#(CLK_PERIOD * 13500000); // Attendre pour vérifier l'arrêt
if (data_available) begin
$display("[%0t ns] Vérification STOP: aucune donnée ne doit être reçue", $time);
#(CLK_PERIOD * 1000);
if (data_available) begin
$display("[%0t ns] ERREUR: Données reçues après STOP", $time);
end else begin
$display("[%0t ns] STOP correct: aucune donnée reçue", $time);
end
end
// Test 4: Commande invalide (8'd4)
$display("=== Test 4: Commande invalide ===");
send_command(8'd4); // Commande invalide
#(CLK_PERIOD * 1000);
if (data_available) begin
$display("[%0t ns] ERREUR: Données reçues pour commande invalide", $time);
end else begin
$display("[%0t ns] Commande invalide ignorée correctement", $time);
end
// Fin de la simulation
$display("==== Fin Test UART Ultrason ====");
#(CLK_PERIOD * 1000);
$stop;
end
endmodule