diff --git a/Semaine_4/UART/src/verilog/top_uart_loopback.v b/Semaine_4/UART/src/verilog/top_uart_loopback.v
index 1721907..4bcfcdf 100644
--- a/Semaine_4/UART/src/verilog/top_uart_loopback.v
+++ b/Semaine_4/UART/src/verilog/top_uart_loopback.v
@@ -50,7 +50,7 @@ module top_uart_loopback (
                 delay_counter <= 0;
 
                 if (rx_received && tx_ready) begin
-                    tx_data <= rx_data;
+                    tx_data <= 8'h31; // Valeur à envoyer
                     state <= WAIT;
 
                     leds[0] <= 0;