From 6bb42700f8a951f8b3a1de05d0743800d0fbbf6e Mon Sep 17 00:00:00 2001 From: Gamenight77 Date: Wed, 7 May 2025 18:05:02 +0200 Subject: [PATCH] Update TX data assignment in UART loopback module to send fixed value --- Semaine_4/UART/src/verilog/top_uart_loopback.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Semaine_4/UART/src/verilog/top_uart_loopback.v b/Semaine_4/UART/src/verilog/top_uart_loopback.v index 1721907..4bcfcdf 100644 --- a/Semaine_4/UART/src/verilog/top_uart_loopback.v +++ b/Semaine_4/UART/src/verilog/top_uart_loopback.v @@ -50,7 +50,7 @@ module top_uart_loopback ( delay_counter <= 0; if (rx_received && tx_ready) begin - tx_data <= rx_data; + tx_data <= 8'h31; // Valeur à envoyer state <= WAIT; leds[0] <= 0;