diff --git a/Semaine_4/FIFO/.gitignore b/Semaine_4/FIFO/.gitignore
new file mode 100644
index 0000000..33b5bda
--- /dev/null
+++ b/Semaine_4/FIFO/.gitignore
@@ -0,0 +1,4 @@
+runs
+.vscode
+workspace.code-workspace
+*.pyc
diff --git a/Semaine_4/FIFO/constraints/top_uart_loopback.cst b/Semaine_4/FIFO/constraints/top_uart_loopback.cst
new file mode 100644
index 0000000..e1fb732
--- /dev/null
+++ b/Semaine_4/FIFO/constraints/top_uart_loopback.cst
@@ -0,0 +1,19 @@
+IO_LOC "rx" 70;
+IO_PORT "rx" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
+IO_LOC "tx" 69;
+IO_PORT "tx" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
+IO_LOC "clk" 4;
+IO_PORT "clk" PULL_MODE=UP BANK_VCCIO=1.8;
+
+IO_LOC "leds[0]" 15;
+IO_PORT "leds[0]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
+IO_LOC "leds[1]" 16;
+IO_PORT "leds[1]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
+IO_LOC "leds[2]" 17;
+IO_PORT "leds[2]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
+IO_LOC "leds[3]" 18;
+IO_PORT "leds[3]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
+IO_LOC "leds[4]" 19;
+IO_PORT "leds[4]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
+IO_LOC "leds[5]" 20;
+IO_PORT "leds[5]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
\ No newline at end of file
diff --git a/Semaine_4/FIFO/project.bat b/Semaine_4/FIFO/project.bat
new file mode 100644
index 0000000..6998748
--- /dev/null
+++ b/Semaine_4/FIFO/project.bat
@@ -0,0 +1,6 @@
+@call c:\oss-cad-suite\environment.bat 
+@echo off
+if "%1"=="sim" call scripts\simulate.bat
+if "%1"=="wave" call scripts\gtkwave.bat
+if "%1"=="clean" call scripts\clean.bat
+if "%1"=="build" call scripts\build.bat
diff --git a/Semaine_4/FIFO/scripts/build.bat b/Semaine_4/FIFO/scripts/build.bat
new file mode 100644
index 0000000..aed8469
--- /dev/null
+++ b/Semaine_4/FIFO/scripts/build.bat
@@ -0,0 +1,45 @@
+@echo off
+setlocal
+
+rem === Aller à la racine du projet ===
+cd /d %~dp0\..
+
+rem === Config de base ===
+set DEVICE=GW2AR-LV18QN88C8/I7
+set BOARD=tangnano20k
+set TOP=top_uart_loopback
+set CST_FILE=%TOP%.cst
+set JSON_FILE=runs/%TOP%.json
+set PNR_JSON=runs/pnr_%TOP%.json
+set BITSTREAM=runs/%TOP%.fs
+
+rem === Créer le dossier runs si nécessaire ===
+if not exist runs (
+    mkdir runs
+)
+
+echo === Étape 1 : Synthèse avec Yosys ===
+yosys -p "read_verilog -sv src/verilog/%TOP%.v src/verilog/uart_rx.v src/verilog/uart_tx.v; synth_gowin -top %TOP% -json %JSON_FILE%"
+if errorlevel 1 goto error
+
+echo === Étape 2 : Placement & Routage avec nextpnr-himbaechel ===
+nextpnr-himbaechel --json %JSON_FILE% --write %PNR_JSON% --device %DEVICE% --vopt cst=constraints/%CST_FILE% --vopt family=GW2A-18C
+if errorlevel 1 goto error
+
+echo === Étape 3 : Packing avec gowin_pack ===
+gowin_pack -d %DEVICE% -o %BITSTREAM% %PNR_JSON%
+if errorlevel 1 goto error
+
+echo === Étape 4 : Flash avec openFPGALoader ===
+openFPGALoader -b %BOARD% %BITSTREAM%
+if errorlevel 1 goto error
+
+echo === Compilation et flash réussis ===
+goto end
+
+:error
+echo === Une erreur est survenue ===
+
+:end
+endlocal
+pause
diff --git a/Semaine_4/FIFO/scripts/clean.bat b/Semaine_4/FIFO/scripts/clean.bat
new file mode 100644
index 0000000..6192ae1
--- /dev/null
+++ b/Semaine_4/FIFO/scripts/clean.bat
@@ -0,0 +1,4 @@
+@echo off
+echo === Nettoyage du dossier runs ===
+rd /s /q runs
+mkdir runs
diff --git a/Semaine_4/FIFO/scripts/gtkwave.bat b/Semaine_4/FIFO/scripts/gtkwave.bat
new file mode 100644
index 0000000..ae1cd1b
--- /dev/null
+++ b/Semaine_4/FIFO/scripts/gtkwave.bat
@@ -0,0 +1,3 @@
+@echo off
+echo === Lancement de GTKWave ===
+gtkwave runs/uart.vcd
diff --git a/Semaine_4/FIFO/scripts/simulate.bat b/Semaine_4/FIFO/scripts/simulate.bat
new file mode 100644
index 0000000..a681db1
--- /dev/null
+++ b/Semaine_4/FIFO/scripts/simulate.bat
@@ -0,0 +1,29 @@
+@echo off
+echo === Simulation avec Icarus Verilog ===
+setlocal enabledelayedexpansion
+
+:: Dossier de sortie
+set OUT=runs/sim.vvp
+
+:: Top-level testbench module
+set TOP=tb_uart
+
+:: Répertoires contenant des fichiers .v
+set DIRS=src/verilog tests/verilog IP/verilog
+
+:: Variable pour stocker les fichiers
+set FILES=
+
+:: Boucle sur chaque dossier
+for %%D in (%DIRS%) do (
+    for %%F in (%%D\*.v) do (
+        set FILES=!FILES! %%F
+    )
+)
+
+:: Compilation avec Icarus Verilog
+iverilog -g2012 -o %OUT% -s %TOP% %FILES%
+
+endlocal
+
+vvp runs/sim.vvp
\ No newline at end of file
diff --git a/Semaine_4/FIFO/src/verilog/fifo.v b/Semaine_4/FIFO/src/verilog/fifo.v
new file mode 100644
index 0000000..9fe96d0
--- /dev/null
+++ b/Semaine_4/FIFO/src/verilog/fifo.v
@@ -0,0 +1,16 @@
+ module uart_tx #(
+	parameter       DETPH = 16,
+	parameter       WIDTH = 8
+)(
+    input wire              clk,
+    input wire              wr_en,
+    input wire[WIDTH-1:0]   wr_data,
+    input wire              rd_en,
+    output wire[WIDTH-1:0]  rd_data,
+
+    output wire             full,
+    output wire             empty,
+);
+
+    
+endmodule
diff --git a/Semaine_4/FIFO/tests/verilog/tb_fifo.v b/Semaine_4/FIFO/tests/verilog/tb_fifo.v
new file mode 100644
index 0000000..f7e6aba
--- /dev/null
+++ b/Semaine_4/FIFO/tests/verilog/tb_fifo.v
@@ -0,0 +1,19 @@
+`timescale 1ns/1ps
+
+module tb_fifo;
+
+    reg clk = 0;
+    
+
+    always #18.5 clk = ~clk;
+
+    
+
+    initial begin
+        $dumpfile("runs/fifo.vcd");
+        $dumpvars(0, tb_fifo);
+
+        
+    end
+
+endmodule
\ No newline at end of file