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Semaine 6 init

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Gamenight77
2025-05-19 09:14:04 +02:00
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177
Semaine_6/UART_ULTRASON_COMMANDS/src/verilog/top_uart_ultrason_command.v Normal file
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module top_uart_ultrason_command (
input wire clk, // 27 MHz
output wire tx,
input wire rx,
inout wire ultrason_sig, // Capteur ultrason
output reg [5:0] leds
);
// === UART RX WIRE ===
wire [7:0] rd_data;
reg rd_en = 0;
wire data_available;
// RX FIFO Instance
uart_rx_fifo uart_rx_inst (
.clk(clk),
.rx_pin(rx),
.rd_data(rd_data),
.rd_en(rd_en),
.data_available(data_available)
);
// === UART TX WIRE ===
reg [7:0] wr_data;
reg wr_en;
wire tx_fifo_full;
// === UART TX FIFO ===
uart_tx_fifo uart_tx_inst (
.clk(clk),
.wr_en(wr_en),
.wr_data(wr_data),
.fifo_full(tx_fifo_full),
.tx_pin(tx)
);
// === Ultrasonic ===
reg start = 0;
wire ultrasonic_busy;
wire [15:0] distance;
wire ultrason_done;
ultrasonic_fpga #(
.CLK_FREQ(27_000_000)
) ultrasonic_inst (
.clk(clk),
.start(start),
.sig(ultrason_sig),
.distance(distance),
.busy(ultrasonic_busy),
.done(ultrason_done)
);
// === FSM ===
localparam IDLE = 0, ONESTART = 1, ONESTOP = 2, CONTINUOUSSTART = 3, CONTINUOUSSTOP = 4, WAIT = 5, NEXT_FIFO = 6;
reg [1:0] command = 0;
reg [31:0] delay_counter = 0;
localparam US_STATE_WIDTH = $clog2(NEXT_FIFO)+1;
reg [US_STATE_WIDTH-1:0] mesure_state = IDLE;
always @(posedge clk) begin
if (data_available) begin
command <= rd_data[1:0];
leds <= rd_data[7:2];
end
end
always @(posedge clk) begin // Mesure state machine
case (mesure_state)
IDLE: begin
if (command == 2'd1 && data_available) begin
mesure_state <= ONESTART;
rd_en <= 1;
end else if (command == 2'd2 && data_available) begin
mesure_state <= CONTINUOUSSTART;
rd_en <= 1;
end else begin
mesure_state <= IDLE;
rd_en <= 0;
end
end
ONESTART: begin
start <= 1;
mesure_state <= ONESTOP;
rd_en <= 0;
end
ONESTOP: begin
start <= 0;
mesure_state <= IDLE;
end
CONTINUOUSSTART: begin
if (command == 3) begin
mesure_state <= NEXT_FIFO;
rd_en <= 1;
end else begin
mesure_state <= CONTINUOUSSTOP;
start <= 1;
rd_en <= 0;
end
end
CONTINUOUSSTOP: begin
start <= 0;
mesure_state <= WAIT;
end
WAIT: begin // Compteur 0.5s
if (delay_counter > 1) begin
delay_counter <= delay_counter - 1;
end else begin
mesure_state <= CONTINUOUSSTART;
delay_counter <= 13500000;
end
end
NEXT_FIFO: begin
rd_en <= 1;
mesure_state <= IDLE;
end
endcase
end
localparam BUSY = 1, SEND_LOW = 2, SEND_HIGH = 3, DONE = 4;
reg [1:0] saver_state = IDLE;
always @(posedge clk) begin // FSM Pour enregistrer la distance
case (saver_state)
IDLE: begin
wr_en <= 0;
if (ultrasonic_busy) begin
saver_state <= BUSY;
end else begin
saver_state <= IDLE;
end
end
BUSY: begin
if (ultrason_done) begin
saver_state <= SEND_LOW;
wr_en <= 1;
wr_data <= distance[7:0];
end else if(ultrasonic_busy) begin
saver_state <= BUSY;
end else begin
saver_state <= IDLE;
end
end
SEND_LOW: begin
wr_en <= 1;
wr_data <= distance[15:8];
saver_state <= SEND_HIGH;
end
SEND_HIGH: begin
wr_en <= 0;
saver_state <= DONE;
end
DONE: begin
wr_data <= 0;
wr_en <= 0;
saver_state <= IDLE;
end
endcase
end
endmodule