diff --git a/Semaine_5/UART_ULTRASON_COMMANDS/tests/verilog/tb_uart_ultrason.v b/Semaine_5/UART_ULTRASON_COMMANDS/tests/verilog/tb_uart_ultrason.v
index b4c2f4e..bd33497 100644
--- a/Semaine_5/UART_ULTRASON_COMMANDS/tests/verilog/tb_uart_ultrason.v
+++ b/Semaine_5/UART_ULTRASON_COMMANDS/tests/verilog/tb_uart_ultrason.v
@@ -3,69 +3,89 @@
 module tb_ultrason_commands;
 
     reg clk = 0;
+    always #18.5 clk = ~clk; // ~27 MHz
+
+    wire tx, rx;
+    wire [5:0] leds;
+    wire ultrason_sig;
+
     reg tx_enable = 0;
-    reg tx_ready;
+    wire tx_ready;
     reg [7:0] data_in = 8'h00;
-    reg [7:0] data_out;
-
-    reg rx_received;
-    wire rx_enable = 1'b1;
-
-    wire rx,tx;
-
-    always #18.5 clk = ~clk;
+    wire [7:0] data_out;
+    wire rx_received;
 
+    // === PARAMÈTRES ===
     localparam CLK_FREQ = 27_000_000;
     localparam BAUD_RATE = 115_200;
 
-    ultrasonic_sensor ultrasonic_sensor_instance (
-        .clk(clk),
-        .signal(ultrason_sig)
-    );
-
-    top_uart_ultrason_command top_uart_ultrason_command_instance (
+    // === MODULE TESTÉ ===
+    top_uart_ultrason_command dut (
         .clk(clk),
         .rx(rx),
         .tx(tx),
         .ultrason_sig(ultrason_sig),
-        .leds()
+        .leds(leds)
     );
 
+    // === SIMULATION CAPTEUR ULTRASON ===
+    ultrasonic_sensor fake_sensor (
+        .clk(clk),
+        .signal(ultrason_sig)
+    );
+
+    // === RX : observe ce que le FPGA envoie ===
     uart_rx #(
         .CLK_FREQ(CLK_FREQ),
         .BAUD_RATE(BAUD_RATE)
-    ) rx_instance (
+    ) uart_rx_inst (
         .clk(clk),
-        .rx_pin(tx),
+        .rx_pin(tx), // observe ce que le FPGA envoie
         .rx_data(data_out),
         .rx_received(rx_received),
-        .rx_enable(rx_enable)
+        .rx_enable(1'b1)
     );
 
+    // === TX : envoie une commande au FPGA ===
     uart_tx #(
         .CLK_FREQ(CLK_FREQ),
         .BAUD_RATE(BAUD_RATE)
-    )tx_instance (
+    ) uart_tx_inst (
         .clk(clk),
         .tx_enable(tx_enable),
         .tx_ready(tx_ready),
         .data(data_in),
-        .tx(rx),
+        .tx(rx), // vers le FPGA
         .rst_p(1'b0)
     );
 
+    // === TEST SEQUENCE ===
     initial begin
-        $dumpfile("runs/uart.vcd");
-        $dumpvars(0, tb_uart);
+        $dumpfile("runs/ultrason_commands.vcd");
+        $dumpvars(0, tb_ultrason_commands);
 
-        $display("======== Start UART ULTRASONIC COMMANDS =========");
+        $display("==== Start UART Ultrasonic Test ====");
 
-        
+        // Attendre que le tx soit prêt
+        wait(tx_ready);
+        #100;
 
-        $display("======== END UART ULTRASONIC COMMANDS =========");
+        // Envoyer la commande "ONE" (1)
+        data_in <= 8'd1; // ONE
+        tx_enable <= 1;
+        #20;
+        tx_enable <= 0;
 
+        // Attendre la réponse
+        wait(rx_received);
+        $display(">> Distance LSB: %d", data_out);
+
+        wait(rx_received);
+        $display(">> Distance MSB: %d", data_out);
+
+        $display("==== End UART Ultrasonic Test ====");
         #1000;
         $stop;
     end
 
-endmodule
\ No newline at end of file
+endmodule