verlan/Verilog_Louis
1
0
Fork 0
forked from tanchou/Verilog
Code Pull Requests Activity

Training exercise

Browse Source
This commit is contained in:
Gamenight77
2025-03-22 18:44:25 +01:00
parent e651a94dbe
commit 7c09418828
5 changed files with 75 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
Introduction/bidouille/Gates4.v Normal file
View File

@@ -0,0 +1,12 @@
module top_module(
input [3:0] in,
output out_and,
output out_or,
output out_xor
);
assign out_and = in[0] & in[1] & in[2] & in[3];
assign out_or = in[0] | in[1] | in[2] | in[3];
assign out_xor = in[0] ^ in[1] ^ in[2] ^ in[3];
endmodule