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forked from tanchou/Verilog

Training exercise

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Gamenight77
2025-03-22 18:44:25 +01:00
parent e651a94dbe
commit 7c09418828
5 changed files with 75 additions and 0 deletions

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module top_module (
input [4:0] a, b, c, d, e, f,
output [7:0] w, x, y, z );//
assign { w, x, y, z } = { a, b, c, d, e, f, 2'b11};
endmodule