diff --git a/Semaine_7/DHT11_UART/IP/verilog/dht11_interface.v b/Semaine_7/DHT11_UART/IP/verilog/dht11_interface.v
index 7c58677..8b6e6ea 100644
--- a/Semaine_7/DHT11_UART/IP/verilog/dht11_interface.v
+++ b/Semaine_7/DHT11_UART/IP/verilog/dht11_interface.v
@@ -22,7 +22,7 @@ module dht11_interface #(
     localparam T_51US          = CLK_FREQ * 58 / 1_000_000;
     localparam T_50US          = CLK_FREQ * 50 / 1_000_000;
     localparam T_49US          = CLK_FREQ * 49 / 1_000_000;
-    localparam T_41US          = CLK_FREQ * 50 / 1_000_000;
+    localparam T_40US          = CLK_FREQ * 40 / 1_000_000;
     localparam T_28US          = CLK_FREQ * 32 / 1_000_000;
     localparam T_26US          = CLK_FREQ * 25 / 1_000_000;
     localparam T_20US          = CLK_FREQ * 18 / 1_000_000;
@@ -154,7 +154,7 @@ module dht11_interface #(
                 if (sig_in == 0) begin
                     
 
-                    raw_data <= {raw_data[38:0], (timer > T_28US)}; // 1 si high > ~28us 
+                    raw_data <= {raw_data[38:0], (timer > T_40US)};
                     timer <= 0;
                     bit_index <= bit_index + 1;
 
@@ -172,14 +172,10 @@ module dht11_interface #(
                 if (raw_data[7:0] == (raw_data[39:32] + raw_data[31:24] + raw_data[23:16] + raw_data[15:8])) begin
                     o_hum_data <= raw_data[39:24];
                     o_temp_data <= raw_data[23:8];
+                    o_checksum <= raw_data[7:0];
                     o_dht11_data_ready <= 1;
                 end 
 
-                o_hum_data <= raw_data[39:24];
-                o_temp_data <= raw_data[23:8];
-                o_checksum <= raw_data[7:0];
-                o_dht11_data_ready <= 1;
-
                 o_busy <= 0;
                 state <= IDLE;
             end