From 83c40bee28c859b067eb175a5775a6ea551c487d Mon Sep 17 00:00:00 2001 From: Gamenight77 Date: Wed, 7 May 2025 10:39:52 +0200 Subject: [PATCH] Fix build script and update state machine in UART loopback module --- Semaine_4/UART/scripts/build.bat | 2 +- .../UART/src/verilog/top_uart_loopback1.v | 178 ++++++++++++++++++ .../IP/verilog/ultrasonic_fpga.v | 1 + .../src/verilog/top_uart_ultrason.v | 2 +- 4 files changed, 181 insertions(+), 2 deletions(-) create mode 100644 Semaine_4/UART/src/verilog/top_uart_loopback1.v diff --git a/Semaine_4/UART/scripts/build.bat b/Semaine_4/UART/scripts/build.bat index f77951c..57bb5a3 100644 --- a/Semaine_4/UART/scripts/build.bat +++ b/Semaine_4/UART/scripts/build.bat @@ -19,7 +19,7 @@ if not exist runs ( ) echo === Étape 1 : Synthèse avec Yosys === -yosys -p "read_verilog -sv src/verilog/%TOP%.v IP/verilog/other_rx.v IP/verilog/other_tx.v src/verilog/uart_rx.v src/verilog/uart_tx.v; synth_gowin -top %TOP% -json %JSON_FILE%" +yosys -p "read_verilog -sv src/verilog/%TOP%1.v IP/verilog/other_rx.v IP/verilog/other_tx.v src/verilog/uart_rx.v src/verilog/uart_tx.v; synth_gowin -top %TOP% -json %JSON_FILE%" if errorlevel 1 goto error echo === Étape 2 : Placement & Routage avec nextpnr-himbaechel === diff --git a/Semaine_4/UART/src/verilog/top_uart_loopback1.v b/Semaine_4/UART/src/verilog/top_uart_loopback1.v new file mode 100644 index 0000000..07f645c --- /dev/null +++ b/Semaine_4/UART/src/verilog/top_uart_loopback1.v @@ -0,0 +1,178 @@ +`default_nettype none +module top_uart_loopback ( + input wire clk, // 27 MHz + input wire rx, + output wire tx, + output wire [5:0] leds +); + + wire rx_received; + wire [7:0] rx_data; + reg [7:0] tx_data; + reg tx_enable; + reg rx_enable; + + wire tx_ready; + +/* // === UART RX === + uart_rx uart_rx_inst ( + .clk(clk), + .rst_p(1'b0), + .rx_pin(rx), + .rx_received(tx_enable), + .rx_received(rx_received), + .rx_enable(1'b1), + .rx_enable(tx_ready), + //.rx_data(rx_data) + .rx_data(rx_data) + );*/ + +reg [7:0] stored_data; + +reg [7:0] data_const = 8'h31; +//initial data_const = ; + +wire r; + + // === UART TX === + uart_tx uart_tx_inst ( + .clk(clk), + .rst_p(1'b0), + .data(data_const), + .tx_enable(tx_enable), + .tx_ready(tx_ready), + .tx(tx) + ); + + /* other_uart_tx uart_tx_inst ( + .clk(clk), + .rst_n(1'b1), + .tx_data(data_const), + .tx_data_valid(tx_enable), + .tx_data_ready(tx_ready), + .tx_pin(tx) + );*/ + + +/* reg delay_active = 0; + reg [31:0] delay_counter = 0; + localparam DELAY_CYCLES = 27000000 / 2; // 0.5 second delay at 27 MHz + reg data_ready = 0; + + + // Store received data and trigger delay + always @(posedge clk) begin + + begin + // Capture new received data + if (rx_received && !data_ready) begin + stored_data <= rx_data; + data_ready <= 1'b1; + delay_active <= 1'b1; + delay_counter <= DELAY_CYCLES; + end + + // Countdown delay + if (delay_active) begin + if (delay_counter > 0) begin + delay_counter <= delay_counter - 1; + end + else begin + delay_active <= 1'b0; + end + end + end + end + + // Control transmission + always @(posedge clk) begin + + begin + tx_enable <= 1'b0; // Default assignment + + // Start transmission when delay completes and UART is ready + if (data_ready && !delay_active && tx_ready && !tx_enable) begin + tx_enable <= 1'b1; + data_ready <= 1'b0; // Clear flag after starting transmission + end + end + end */ + + +localparam CLK_FREQ = 27_000_000; // 27 MHz +localparam DATA_BYTE = 8'h31; // ASCII '1' + + // State machine to continuously send the byte + reg [31:0] delay_counter; + localparam DELAY_CYCLES = CLK_FREQ / 2; // 0.5 second delay between transmissions + + always @(posedge clk) begin + begin + // Default assignments + tx_enable <= 1'b0; + + if (tx_ready && delay_counter == 0) begin + // Start new transmission + tx_enable <= 1'b1; + data_const <= DATA_BYTE; + delay_counter <= DELAY_CYCLES; + end + else if (delay_counter > 0) begin + // Count down delay + delay_counter <= delay_counter - 1; + end + end + end + + + + +/* + // === FSM avec délai === + localparam IDLE = 0, WAIT = 1, SEND = 2; + reg [1:0] state = IDLE; + reg [8:0] delay_counter = 0; + + always @(posedge clk) begin + leds[5] <= rx; + leds[4] <= tx; + + case (state) + IDLE: begin + tx_enable <= 0; + delay_counter <= 0; + + if (rx_received && tx_ready) begin + tx_data <= rx_data; + state <= WAIT; + leds[0] <= 0; + leds[1] <= 1; + end + end + + WAIT: begin + delay_counter <= delay_counter + 1; + + if (delay_counter == 8'd400 && tx_ready) begin + tx_enable <= 1; + state <= SEND; + end else begin + tx_enable <= 0; + end + + leds[0] <= 1; + leds[1] <= 0; + end + + + SEND: begin + tx_enable <= 0; + state <= IDLE; + + leds[0] <= 0; + leds[1] <= 0; // Envoi terminé + end + endcase + end +*/ +endmodule \ No newline at end of file diff --git a/Semaine_4/UART_ULTRASON/IP/verilog/ultrasonic_fpga.v b/Semaine_4/UART_ULTRASON/IP/verilog/ultrasonic_fpga.v index fdf4280..7394173 100644 --- a/Semaine_4/UART_ULTRASON/IP/verilog/ultrasonic_fpga.v +++ b/Semaine_4/UART_ULTRASON/IP/verilog/ultrasonic_fpga.v @@ -53,6 +53,7 @@ module ultrasonic_fpga #( case (state) IDLE: begin + done <= 1; sig_out <= 0; sig_dir <= 0; distance <= 0; diff --git a/Semaine_4/UART_ULTRASON/src/verilog/top_uart_ultrason.v b/Semaine_4/UART_ULTRASON/src/verilog/top_uart_ultrason.v index 5b1f3eb..2b66010 100644 --- a/Semaine_4/UART_ULTRASON/src/verilog/top_uart_ultrason.v +++ b/Semaine_4/UART_ULTRASON/src/verilog/top_uart_ultrason.v @@ -56,7 +56,7 @@ module top_uart_ultrason ( SEND_LOW: begin wr_en <= 1; wr_data <= distance[7:0]; // Octet LSB - state <= IDLE; + state <= SEND_HIGH; end SEND_HIGH: begin