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Refactor uart_top module: streamline code structure and improve readability by removing unused variables and simplifying instantiation

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Gamenight77
2025-04-22 15:44:04 +02:00
parent 5f3568ff9b
commit 8641f618f0
1 changed files with 41 additions and 112 deletions
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123
Semaine_1/UARTV2/top_uart_rx_tx.v
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@@ -1,119 +1,48 @@
module uart_top(
input clk,
input rst,
input uart_rx,
output uart_tx
input wire clk,
input wire rst,
input wire uart_rx,
output wire uart_tx,
// Interfaces RX
output wire [7:0] rx_data,
output wire rx_data_valid,
input wire rx_data_ready,
// Interfaces TX
input wire [7:0] tx_data,
input wire tx_data_valid,
output wire tx_data_ready
);
parameter CLK_FRE = 27_000_000; // Mhz
parameter UART_FRE = 115200; // Baud
parameter CLK_FRE = 27_000_000; // Hz
parameter UART_FRE = 115200; // Baudrate
localparam IDLE = 0;
localparam SEND = 1; // send
localparam WAIT = 2; // wait 1 second and send uart received data
reg[7:0] tx_data;
reg[7:0] tx_str;
reg tx_data_valid;
wire tx_data_ready;
reg[7:0] tx_cnt;
wire[7:0] rx_data;
wire rx_data_valid;
wire rx_data_ready;
reg[31:0] wait_cnt;
reg[3:0] state;
wire rst_p = rst;
assign rx_data_ready = 1'b1; //always can receive data,
always@(posedge clk or negedge rst_p)
begin
if(rst_p == 1'b1)
begin
wait_cnt <= 32'd0;
tx_data <= 8'd0;
state <= IDLE;
tx_cnt <= 8'd0;
tx_data_valid <= 1'b0;
end
else
case(state)
IDLE:begin
state <= SEND;
end
SEND:begin
wait_cnt <= 32'd0;
tx_data <= tx_str;
if(tx_data_valid == 1'b1 && tx_data_ready == 1'b1 && tx_cnt < DATA_NUM - 1)//Send 12 bytes data
begin
tx_cnt <= tx_cnt + 8'd1; //Send data counter
end
else if(tx_data_valid && tx_data_ready)//last byte sent is complete
begin
tx_cnt <= 8'd0;
tx_data_valid <= 1'b0;
state <= WAIT;
end
else if(~tx_data_valid)
begin
tx_data_valid <= 1'b1;
end
end
WAIT:begin
wait_cnt <= wait_cnt + 32'd1;
if(rx_data_valid == 1'b1)
begin
tx_data_valid <= 1'b1;
tx_data <= rx_data; // send uart received data
end
else if(tx_data_valid && tx_data_ready)
begin
tx_data_valid <= 1'b0;
end
else if(wait_cnt >= CLK_FRE * 1000_000) // wait for 1 second
state <= SEND;
end
default:
state <= IDLE;
endcase
end
always@(*)
tx_str <= send_data[(DATA_NUM - 1 - tx_cnt) * 8 +: 8];
uart_rx#
(
// === Instanciation RX ===
uart_rx #(
.CLK_FRE(CLK_FRE),
.BAUD_RATE(UART_FRE)
) uart_rx_inst
(
) uart_rx_inst (
.clk (clk),
.rst_p (rst_p),
.rst_p (rst),
.rx_data (rx_data),
.rx_data_valid (rx_data_valid),
.rx_data_ready (rx_data_ready),
.rx_pin (uart_rx)
);
uart_tx#
(
// === Instanciation TX ===
uart_tx #(
.CLK_FRE(CLK_FRE),
.BAUD_RATE(UART_FRE)
) uart_tx_inst
(
) uart_tx_inst (
.clk (clk),
.rst_p (rst_p),
.rst_p (rst),
.tx_data (tx_data),
.tx_data_valid (tx_data_valid),
.tx_data_ready (tx_data_ready),
.tx_pin (uart_tx)
);
endmodule