diff --git a/Semaine_4/UART/scripts/gtkwave.bat b/Semaine_4/UART/scripts/gtkwave.bat
index 8ea87be..ae1cd1b 100644
--- a/Semaine_4/UART/scripts/gtkwave.bat
+++ b/Semaine_4/UART/scripts/gtkwave.bat
@@ -1,3 +1,3 @@
 @echo off
 echo === Lancement de GTKWave ===
-gtkwave runs/uart_rx.vcd
+gtkwave runs/uart.vcd
diff --git a/Semaine_4/UART/scripts/simulate.bat b/Semaine_4/UART/scripts/simulate.bat
index fd6311a..a681db1 100644
--- a/Semaine_4/UART/scripts/simulate.bat
+++ b/Semaine_4/UART/scripts/simulate.bat
@@ -6,7 +6,7 @@ setlocal enabledelayedexpansion
 set OUT=runs/sim.vvp
 
 :: Top-level testbench module
-set TOP=tb_uart_rx
+set TOP=tb_uart
 
 :: Répertoires contenant des fichiers .v
 set DIRS=src/verilog tests/verilog IP/verilog
diff --git a/Semaine_4/UART/tests/verilog/tb_uart.v b/Semaine_4/UART/tests/verilog/tb_uart.v
new file mode 100644
index 0000000..0788abc
--- /dev/null
+++ b/Semaine_4/UART/tests/verilog/tb_uart.v
@@ -0,0 +1,84 @@
+`timescale 1ns/1ps
+
+module tb_uart;
+
+    reg clk = 0;
+    reg tx_enable = 0;
+    reg tx_ready;
+    reg [7:0] data_in = 8'h00;
+    reg [7:0] data_out;
+
+    reg rx_received;
+    wire rx_enable = 1'b1;
+
+    wire pin;
+
+    always #18.5 clk = ~clk;
+
+    localparam CLK_FREQ = 27_000_000;
+    localparam BAUD_RATE = 115_200;
+
+    uart_rx #(
+        .CLK_FREQ(CLK_FREQ),
+        .BAUD_RATE(BAUD_RATE)
+    ) rx_instance (
+        .clk(clk),
+        .rx_pin(pin),
+        .rx_data(data_out),
+        .rx_received(rx_received),
+        .rx_enable(rx_enable)
+    );
+
+    uart_tx #(
+        .CLK_FREQ(CLK_FREQ),
+        .BAUD_RATE(BAUD_RATE)
+    )tx_instance (
+        .clk(clk),
+        .tx_enable(tx_enable),
+        .tx_ready(tx_ready),
+        .data(data_in),
+        .tx(pin),
+        .rst_p(1'b0)
+    );
+
+    initial begin
+        $dumpfile("runs/uart.vcd");
+        $dumpvars(0, tb_uart);
+
+        $display("======== Start UART LOOPBACK test =========");
+
+        #100;
+
+        data_in <= 8'd234;   // 234
+        tx_enable <= 1;
+        wait(tx_ready == 1'b0); 
+        tx_enable <= 0; 
+
+        // Attendre
+        wait (rx_received == 1'b1); // Attendre que le signal de reception soit actif
+
+        $display("Data received: %d", data_out); // Afficher la valeur recu
+        $display("Data expected: %d", data_in); // Afficher la valeur envoyee
+
+        #1000;
+
+        wait(tx_ready == 1'b1); // Attendre que le signal de reception soit actif
+
+        data_in <= 8'd202;   // 202
+        tx_enable <= 1;
+        wait(tx_ready == 1'b0); 
+        tx_enable <= 0; 
+
+        // Attendre
+        wait (rx_received == 1'b1); // Attendre que le signal de reception soit actif
+
+        $display("Data received: %d", data_out); // Afficher la valeur recu
+        $display("Data expected: %d", data_in); // Afficher la valeur envoyee
+
+        $display("======== END UART TX test =========");
+
+        #1000;
+        $stop;
+    end
+
+endmodule
\ No newline at end of file