forked from tanchou/Verilog
Refactor ultrasonic_fpga module: update distance output and state handling; add top_ultrason_uart module for integration with UART and ultrasonic sensor
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@@ -1,9 +1,10 @@
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module uart_tx(
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input wire clk,
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input wire start, // Signal de démarrage de la transmission
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input wire [7:0] data, // Données à transmettre
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output reg tx = 1, // Sortie de transmission
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output reg busy = 0 // Indicateur de transmission en cours
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input wire clk,
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input wire start,
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input wire [7:0] data,
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output reg tx = 1,
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output reg busy = 0
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);
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parameter CLK_FREQ = 27_000_000;
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