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forked from tanchou/Verilog

Refactor ultrasonic_fpga module: update distance output and state handling; add top_ultrason_uart module for integration with UART and ultrasonic sensor

This commit is contained in:
Gamenight77
2025-04-17 13:02:47 +02:00
parent 8c1b452487
commit 897f829e40
3 changed files with 64 additions and 9 deletions

View File

@@ -1,9 +1,10 @@
module uart_tx(
input wire clk,
input wire start, // Signal de démarrage de la transmission
input wire [7:0] data, // Données à transmettre
output reg tx = 1, // Sortie de transmission
output reg busy = 0 // Indicateur de transmission en cours
input wire clk,
input wire start,
input wire [7:0] data,
output reg tx = 1,
output reg busy = 0
);
parameter CLK_FREQ = 27_000_000;