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leds

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Louis TANCHOU
2025-05-26 11:19:03 +02:00
parent cac1a38dad
commit 92144d315e
1 changed files with 1 additions and 1 deletions
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Semaine_7/DHT11_UART/src/verilog/dht11_uart_top.v
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@@ -60,7 +60,7 @@ always_ff @(posedge clk) begin
strobe2s <= 0; strobe2s <= 0;
end end
leds[5] <= o_dht11_error; leds[5] <= !o_dht11_error;
end end
always_ff @(posedge clk) begin always_ff @(posedge clk) begin