From 93e0e96798531068fcc2ccc7d837713793f65506 Mon Sep 17 00:00:00 2001 From: Gamenight77 Date: Wed, 7 May 2025 18:07:45 +0200 Subject: [PATCH] Add WAIT state to FSM and implement delay mechanism in UART module --- .../UART_ULTRASON/src/verilog/top_uart_ultrason.v | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/Semaine_4/UART_ULTRASON/src/verilog/top_uart_ultrason.v b/Semaine_4/UART_ULTRASON/src/verilog/top_uart_ultrason.v index 2b66010..85a7612 100644 --- a/Semaine_4/UART_ULTRASON/src/verilog/top_uart_ultrason.v +++ b/Semaine_4/UART_ULTRASON/src/verilog/top_uart_ultrason.v @@ -37,9 +37,11 @@ module top_uart_ultrason ( ); // === FSM === - localparam IDLE = 0, SEND_LOW = 2, SEND_HIGH = 3; + localparam IDLE = 0, WAIT = 1 ,SEND_LOW = 2, SEND_HIGH = 3; reg [1:0] state = IDLE; + reg [8:0] delay_counter = 0; + always @(posedge clk) begin // Activer en continu tant que FIFO pas pleine start <= 1; @@ -61,7 +63,16 @@ module top_uart_ultrason ( SEND_HIGH: begin wr_data <= distance[15:8]; // Octet MSB - state <= IDLE; + state <= WAIT; + end + + WAIT: begin // Code non testé + if (delay_counter < 1000000) begin + delay_counter <= delay_counter + 1; + end else begin + state <= IDLE; + delay_counter <= 0; + end end endcase