From 99e259f672ea5d30bbf8af5992aab921183f5cc4 Mon Sep 17 00:00:00 2001
From: Gamenight77 <game.night.77176@gmail.com>
Date: Fri, 9 May 2025 10:27:13 +0200
Subject: [PATCH] MAJ FIFO -> turn wire rd_data into register

---
 Semaine_4/FIFO/src/verilog/fifo.v              | 18 +++++++++---------
 .../UART/src/verilog/top_uart_loopback1.v      |  4 +---
 2 files changed, 10 insertions(+), 12 deletions(-)

diff --git a/Semaine_4/FIFO/src/verilog/fifo.v b/Semaine_4/FIFO/src/verilog/fifo.v
index 4d50720..031be59 100644
--- a/Semaine_4/FIFO/src/verilog/fifo.v
+++ b/Semaine_4/FIFO/src/verilog/fifo.v
@@ -1,25 +1,24 @@
  module fifo #(
-	parameter       DETPH = 16,
+	parameter       SIZE = 16,
 	parameter       WIDTH = 8
 )(
     input wire              clk,
     input wire              wr_en,
     input wire[WIDTH-1:0]   wr_data,
     input wire              rd_en,
-    output wire[WIDTH-1:0]  rd_data,
+    output reg[WIDTH-1:0]   rd_data,
 
     output wire             full,
     output wire             empty
 );
 
-    reg [WIDTH-1:0]         fifo[0:DETPH-1];
+    reg [WIDTH-1:0]         fifo[0:SIZE-1];
     reg [3:0]               wr_ptr;
     reg [3:0]               rd_ptr;
     reg [3:0]               count;
 
-    assign full = (count == DETPH);
+    assign full = (count == SIZE);
     assign empty = (count == 0);
-    assign rd_data = fifo[rd_ptr];
 
     initial begin
         wr_ptr = 0;
@@ -27,15 +26,16 @@
         count = 0;
     end
 
-    always @(posedge clk) begin
+    always @(posedge clk) begin // IN
         if (wr_en && !full) begin
             fifo[wr_ptr] <= wr_data;
-            wr_ptr <= (wr_ptr + 1) % DETPH;
+            wr_ptr <= (wr_ptr + 1) % SIZE;
             count <= count + 1;
         end
 
-        if (rd_en && !empty) begin
-            rd_ptr <= (rd_ptr + 1) % DETPH;
+        if (rd_en && !empty) begin // OUT
+            rd_ptr <= (rd_ptr + 1) % SIZE;
+            rd_data <= fifo[rd_ptr];
             count <= count - 1;
         end
     end
diff --git a/Semaine_4/UART/src/verilog/top_uart_loopback1.v b/Semaine_4/UART/src/verilog/top_uart_loopback1.v
index ac08270..e9d38f3 100644
--- a/Semaine_4/UART/src/verilog/top_uart_loopback1.v
+++ b/Semaine_4/UART/src/verilog/top_uart_loopback1.v
@@ -120,13 +120,11 @@ localparam DATA_BYTE = 8'h31; // ASCII '1'
             tx_enable <= 1'b0;
             leds[5:0] <= rx_data[5:0];
             
-            if (tx_ready && delay_counter == 0) begin
+            if (tx_ready && rx_received) begin
                 // Start new transmission
                 tx_enable <= 1'b1;
                 data_const <= DATA_BYTE;
                 tx_data <= rx_data; 
-
-                 // Display received data on LEDs
             
                 delay_counter <= DELAY_CYCLES;
             end