From a00122b595c87eceec560553b07f2571e6c4010a Mon Sep 17 00:00:00 2001 From: Gamenight77 Date: Wed, 16 Apr 2025 13:32:08 +0200 Subject: [PATCH] Fix clock period comment in testbench for clarity --- Semaine 1/Ultrasonic/tb_ultrasonic_fpga.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Semaine 1/Ultrasonic/tb_ultrasonic_fpga.v b/Semaine 1/Ultrasonic/tb_ultrasonic_fpga.v index bea169f..b2382b6 100644 --- a/Semaine 1/Ultrasonic/tb_ultrasonic_fpga.v +++ b/Semaine 1/Ultrasonic/tb_ultrasonic_fpga.v @@ -11,7 +11,7 @@ module tb_ultrasonic_fpga; time t_start, t_end; - // Clock 27MHz => periode = 37.037ns + // Clock 27MHz => periode = 37ns always #18 clk = ~clk; ultrasonic_fpga uut (