verlan/Verilog_Louis
1
0
Fork 0
forked from tanchou/Verilog
Code Pull Requests Activity

init semaine 7

Browse Source
This commit is contained in:
Gamenight77
2025-05-25 19:04:56 +02:00
parent 4c3e40b266
commit a02d6e7d22
36 changed files with 1900 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

24
Semaine_7/DHT11/constraints/dht11_interface.cst Normal file
View File

@@ -0,0 +1,24 @@
IO_LOC "tx" 69;
IO_PORT "tx" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
IO_LOC "rx" 70;
IO_PORT "rx" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
IO_LOC "clk" 4;
IO_PORT "clk" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
IO_LOC "ultrason_sig" 73;
IO_PORT "ultrason_sig" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
IO_LOC "leds[0]" 15;
IO_PORT "leds[0]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "leds[1]" 16;
IO_PORT "leds[1]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "leds[2]" 17;
IO_PORT "leds[2]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "leds[3]" 18;
IO_PORT "leds[3]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "leds[4]" 19;
IO_PORT "leds[4]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "leds[5]" 20;
IO_PORT "leds[5]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;