forked from tanchou/Verilog
init semaine 7
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Gamenight77
213
Semaine_7/DHT11/src/verilog/dht11_interface.v
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213
Semaine_7/DHT11/src/verilog/dht11_interface.v
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@@ -0,0 +1,213 @@
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module dht11_interface #(
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parameter CLK_FREQ = 27_000_000
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)(
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input wire i_clk,
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inout wire io_dht11_sig,
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input wire i_start,
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output reg o_dht11_data_ready,
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output reg o_busy,
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output reg [7:0] o_temp_data,
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output reg [7:0] o_hum_data,
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output reg o_dht11_error
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);
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// === DHT11 INTERFACE ===
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// === PARAMÈTRES ===
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localparam T_18MS = CLK_FREQ * 18 / 1_000; // cycles pour 18ms a partir
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localparam T_80US = CLK_FREQ * 81 / 1_000_000;
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localparam T_79US = CLK_FREQ * 79 / 1_000_000;
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localparam T_71US = CLK_FREQ * 71 / 1_000_000;
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localparam T_51US = CLK_FREQ * 51 / 1_000_000;
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localparam T_50US = CLK_FREQ * 50 / 1_000_000;
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localparam T_49US = CLK_FREQ * 49 / 1_000_000;
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localparam T_41US = CLK_FREQ * 41 / 1_000_000;
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localparam T_28US = CLK_FREQ * 28 / 1_000_000;
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localparam T_26US = CLK_FREQ * 26 / 1_000_000;
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localparam T_20US = CLK_FREQ * 20 / 1_000_000;
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// === Signal bidirectionnel ===
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reg sig_dir;
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reg sig_out;
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wire sig_in;
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assign io_dht11_sig = sig_dir ? sig_out : 1'bz; // Si sig_dir = 1, on force la valeur de sig_out sur la ligne, sinon on laisse la ligne libre (1'bz)
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assign sig_in = io_dht11_sig;
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// === REGISTRES ===
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reg [3:0] state;
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reg [31:0] timer;
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reg [7:0] temp_data, hum_data;
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reg [7:0] temp_dec, hum_dec, checksum;
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reg [2:0] bit_count;
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reg [5:0] bit_index;
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reg [39:0] raw_data;
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// === FSM ===
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localparam IDLE = 4'd0, // Pull up la ligne
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START = 4'd1, // Pull low 18ms
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WAIT_RESPONSE = 4'd2, // Release la ligne (entre 20 et 40us)
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RESPONSE_LOW = 4'd3, // DHT11 pull low 80us
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RESPONSE_HIGH = 4'd4, // DHT11 pull high 80us
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READ_BITS_LOW = 4'd5,
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READ_BITS_HIGH = 4'd6,
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DONE = 4'd7,
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ERROR = 4'd8;
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// === INITIALISATION ===
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initial begin
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sig_dir = 0;
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sig_out = 1;
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timer = 0;
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state = IDLE;
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bit_index = 0;
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raw_data = 0;
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o_dht11_data_ready = 0;
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o_dht11_error = 0;
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end
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// === FSM principale ===
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always @(posedge i_clk) begin
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case (state)
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IDLE: begin
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sig_dir <= 0;
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//sig_out <= 1;
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timer <= 0;
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bit_index <= 0;
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raw_data <= 0;
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o_busy <= 0;
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if (i_start) begin
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sig_dir <= 1;
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sig_out <= 0;
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timer <= 0;
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o_busy <= 1;
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state <= START;
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o_dht11_data_ready <= 0;
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o_dht11_error <= 0;
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end
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end
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START: begin
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timer <= timer + 1;
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if (timer >= T_18MS) begin
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sig_dir <= 0; // libérer la ligne
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timer <= 0;
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state <= WAIT_RESPONSE;
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end
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end
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WAIT_RESPONSE: begin
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timer <= timer + 1;
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if (sig_in == 0) begin
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if (timer > T_20US && timer < T_41US) begin
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state <= RESPONSE_LOW;
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timer <= 0;
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end else begin
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state <= ERROR;
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end
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end else if (timer > T_41US) begin
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state <= ERROR;
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end
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end
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RESPONSE_LOW: begin
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timer <= timer + 1;
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if (sig_in == 1) begin
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if (timer > T_79US && timer < T_80US) begin
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timer <= 0;
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state <= RESPONSE_HIGH;
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end else begin
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state <= ERROR;
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end
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end else if (timer > T_80US) begin
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state <= ERROR;
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end
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end
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RESPONSE_HIGH: begin
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timer <= timer + 1;
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if (sig_in == 0) begin
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if (timer > T_79US && timer < T_80US) begin
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timer <= 0;
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state <= READ_BITS_LOW;
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end else begin
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state <= ERROR;
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end
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end else if (timer > T_80US) begin
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state <= ERROR;
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end
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end
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READ_BITS_LOW: begin
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timer <= timer + 1;
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if (sig_in == 1) begin
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if (timer > T_49US && timer < T_51US) begin
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timer <= 0;
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state <= READ_BITS_HIGH;
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end else begin
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state <= ERROR;
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end
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end else if (timer > T_51US) begin
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state <= ERROR;
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end
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end
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READ_BITS_HIGH: begin // entre 26 et 28us = 0 et ~70us = 1
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timer <= timer + 1;
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if (sig_in == 0) begin
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if (timer <= T_26US) begin
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state <= ERROR;
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end
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raw_data <= {raw_data[38:0], (timer > T_28US)}; // 1 si high > ~28us
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timer <= 0;
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bit_index <= bit_index + 1;
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if (bit_index == 39) begin // Code a testé ici pour etre sur de capter le dernier bit
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state <= DONE;
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end else begin
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state <= READ_BITS_LOW;
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end
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end else if (timer > T_71US) begin
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state <= ERROR;
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end
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end
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DONE: begin
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hum_data <= raw_data[39:32];
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hum_dec <= raw_data[31:24];
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temp_data <= raw_data[23:16];
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temp_dec <= raw_data[15:8];
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checksum <= raw_data[7:0];
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if (raw_data[7:0] == (raw_data[39:32] + raw_data[31:24] + raw_data[23:16] + raw_data[15:8])) begin
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o_hum_data <= raw_data[39:32];
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o_temp_data <= raw_data[23:16];
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o_dht11_data_ready <= 1;
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end else begin
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o_dht11_error <= 1;
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end
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o_busy <= 0;
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state <= IDLE;
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end
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ERROR: begin
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o_dht11_error <= 1;
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state <= IDLE;
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end
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endcase
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end
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endmodule
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174
Semaine_7/DHT11/src/verilog/dht11_model.v
Normal file
174
Semaine_7/DHT11/src/verilog/dht11_model.v
Normal file
@@ -0,0 +1,174 @@
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module dht11_model #(
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parameter CLK_FREQ = 27_000_000
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)
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(
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inout wire data, // Ligne de données bidirectionnelle
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input wire clk, // Horloge système (27 MHz)
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input wire rst_n // Reset actif bas
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);
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// Paramètres pour les timings (basés sur une horloge de 27 MHz, période ~37 ns)
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localparam integer CLK_PERIOD_NS = (1_000_000_000 / CLK_FREQ); // 37 ns
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localparam T_START_LOW = (17_000_000 / CLK_PERIOD_NS); // 17 ms (ajusté selon votre code)
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localparam T_START_HIGH = (40_000 / CLK_PERIOD_NS); // 40 µs
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localparam T_RESP_LOW = (80_000 / CLK_PERIOD_NS); // 80 µs
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localparam T_RESP_HIGH = (80_000 / CLK_PERIOD_NS); // 80 µs
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localparam T_BIT_LOW = (50_000 / CLK_PERIOD_NS); // 50 µs pour le signal LOW de chaque bit
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localparam T_BIT0_HIGH = (27_000 / CLK_PERIOD_NS); // 26 µs pour le signal HIGH d'un bit '0'
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localparam T_BIT1_HIGH = (70_000 / CLK_PERIOD_NS); // 70 µs pour le signal HIGH d'un bit '1'
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localparam T_BIT_GAP = (50_000 / CLK_PERIOD_NS); // 50 µs entre bits
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localparam DATA_BITS = 40; // 40 bits de données
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// États de la machine à états de Moore
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localparam IDLE = 4'd0,
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WAIT_START_LOW = 4'd1,
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WAIT_START_HIGH= 4'd2,
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RESPONSE_LOW = 4'd3,
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RESPONSE_HIGH = 4'd4,
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SEND_BIT_LOW = 4'd5,
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SEND_BIT_HIGH = 4'd6,
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END_TRANS = 4'd7,
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LAST_BIT_LOW = 4'd8;
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// Signaux internes
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reg [3:0] state; // État actuel
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reg [31:0] counter; // Compteur pour les timings (supporte jusqu'à 20 ms)
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reg [5:0] bit_index; // Index du bit à envoyer
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reg data_out; // Valeur de sortie sur la ligne data
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reg data_oe; // Output enable (1 = sortie, 0 = haute impédance)
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wire data_in; // Valeur lue sur la ligne data
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// Données simulées (exemple : humidité = 45.0%, température = 23.0°C)
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reg [7:0] humidity_int = 8'h2D; // 45 en décimal
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reg [7:0] humidity_dec = 8'h00; // 0
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reg [7:0] temp_int = 8'h17; // 23 en décimal
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reg [7:0] temp_dec = 8'h00; // 0
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reg [7:0] checksum; // Checksum
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reg [39:0] data_shift; // Registre pour les 40 bits de données
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// Gestion de la ligne bidirectionnelle
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assign data = data_oe ? data_out : 1'bz;
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assign data_in = data;
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// Calcul du checksum et préparation des données
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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checksum <= 8'h00;
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data_shift <= 40'b0;
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end else begin
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checksum <= humidity_int + humidity_dec + temp_int + temp_dec;
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data_shift <= {humidity_int, humidity_dec, temp_int, temp_dec, checksum};
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end
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end
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// Logique séquentielle (machine à états de Moore)
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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state <= IDLE;
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counter <= 32'b0;
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bit_index <= 6'b0;
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data_out <= 1'b1;
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data_oe <= 1'b0;
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end else begin
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counter <= counter + 1; // Incrément du compteur par défaut
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// assert (bit_index < DATA_BITS) else $error("Index out of bounds: %d", bit_index);
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case (state)
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IDLE: begin
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counter <= 32'b0;
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bit_index <= 6'b0;
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data_out <= 1'b1;
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data_oe <= 1'b0;
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if (data_in === 1'b0) begin
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state <= WAIT_START_LOW;
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end
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end
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WAIT_START_LOW: begin
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data_out <= 1'b1;
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data_oe <= 1'b0;
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if (data_in === 1'b1 && counter >= T_START_LOW) begin
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state <= WAIT_START_HIGH;
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counter <= 32'b0;
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$display("17ms");
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end else if (data_in === 1'b1) begin
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state <= IDLE; // Signal de démarrage trop court
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end
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end
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WAIT_START_HIGH: begin
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data_out <= 1'b1;
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data_oe <= 1'b0;
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if (counter >= T_START_HIGH) begin
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state <= RESPONSE_LOW;
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counter <= 32'b0;
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end
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end
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RESPONSE_LOW: begin
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data_out <= 1'b0;
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data_oe <= 1'b1;
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if (counter >= T_RESP_LOW) begin
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state <= RESPONSE_HIGH;
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counter <= 32'b0;
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end
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end
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RESPONSE_HIGH: begin
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data_out <= 1'b1;
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data_oe <= 1'b1;
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if (counter >= T_RESP_HIGH) begin
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counter <= 32'b0;
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state <= SEND_BIT_LOW;
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end
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end
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SEND_BIT_LOW: begin
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data_out <= 1'b0;
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data_oe <= 1'b1;
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if (counter >= T_BIT_LOW) begin
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state <= SEND_BIT_HIGH;
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counter <= 32'b0;
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end
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end
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SEND_BIT_HIGH: begin
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data_out <= 1'b1;
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data_oe <= 1'b1;
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if (counter >= (data_shift[39-bit_index] ? T_BIT1_HIGH : T_BIT0_HIGH)) begin
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counter <= 32'b0;
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bit_index <= bit_index + 1;
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if (bit_index + 1 < DATA_BITS) begin
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state <= SEND_BIT_LOW;
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end else begin
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state <= LAST_BIT_LOW;
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bit_index <= 6'b0;
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counter <= 32'b0;
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end
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end
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end
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LAST_BIT_LOW: begin
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data_out <= 1'b0;
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data_oe <= 1'b1;
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if (counter >= T_BIT_LOW) begin
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state <= END_TRANS;
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counter <= 32'b0;
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end
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end
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END_TRANS: begin
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data_out <= 1'b1;
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data_oe <= 1'b0;
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counter <= 32'b0;
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state <= IDLE;
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end
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default: begin
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state <= IDLE;
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counter <= 32'b0;
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data_out <= 1'b1;
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data_oe <= 1'b0;
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end
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endcase
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end
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end
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endmodule
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