forked from tanchou/Verilog
init semaine 7
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8
Semaine_7/DHT11_UART/constraints/dht11_uart_top.cst
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8
Semaine_7/DHT11_UART/constraints/dht11_uart_top.cst
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@@ -0,0 +1,8 @@
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IO_LOC "tx" 69;
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IO_PORT "tx" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
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IO_LOC "clk" 4;
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IO_PORT "clk" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
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IO_LOC "io_dht11_sig" 73;
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IO_PORT "io_dht11_sig" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
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