forked from tanchou/Verilog
init semaine 7
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25
Semaine_7/DHT11_UART/scripts/linux/upload.sh
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25
Semaine_7/DHT11_UART/scripts/linux/upload.sh
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#!/bin/bash
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# Aller à la racine du projet
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cd "$(dirname "$0")/../.." || exit 1
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# Config de base
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DEVICE="GW2AR-LV18QN88C8/I7"
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BOARD="tangnano20k"
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TOP="dht11_uart_top"
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CST_FILE="$TOP.cst"
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JSON_FILE="runs/$TOP.json"
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PNR_JSON="runs/pnr_$TOP.json"
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BITSTREAM="runs/$TOP.fs"
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# Créer le dossier runs si nécessaire
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mkdir -p runs
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echo "=== Étape 4 : Flash avec openFPGALoader ==="
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sudo /etc/oss-cad-suite/bin/openFPGALoader -b "$BOARD" "$BITSTREAM"
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if [ $? -ne 0 ]; then
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echo "=== Erreur lors du flash ==="
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exit 1
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fi
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echo "=== Compilation et flash réussis ==="
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