init semaine 7

Semaine_7/DHT11_UART/src/verilog/dht11_uart_top.v

@@ -0,0 +1,104 @@
+`default_nettype none
+module dht11_uart_top (
+    input clk,
+    inout io_dht11_sig,
+    output tx
+);
+
+localparam CLK_FREQ = 27_000_000; // 27 MHz
+
+reg [7:0] wr_data;
+reg wr_en;
+wire tx_fifo_full;
+
+
+reg i_start;
+wire o_dht11_data_ready;
+wire o_busy;
+wire [7:0] o_temp_data;
+wire [7:0] o_hum_data;
+wire o_dht11_error;
+
+uart_tx_fifo #(
+    .CLK_FREQ(CLK_FREQ),
+    .BAUD_RATE(115200),
+    .FIFO_SIZE(8)
+) uart_tx_inst (
+    .clk(clk),
+    .wr_en(wr_en),
+    .wr_data(wr_data),
+    .fifo_full(tx_fifo_full),
+    .tx_pin(tx)
+);
+
+dht11_interface dht11_inst (
+    .i_clk(clk),
+    .io_dht11_sig(io_dht11_sig),
+    .i_start(i_start),
+    .o_dht11_data_ready(o_dht11_data_ready),
+    .o_busy(o_busy),
+    .o_temp_data(o_temp_data),
+    .o_hum_data(o_hum_data),
+    .o_dht11_error(o_dht11_error)
+);
+
+// === FSM ===
+localparam X=4, WAIT = 0, MESURE = 1, SEND_FIFO1 = 2, SEND_FIFO2 = 3;
+reg [2:0] state = X;
+reg [31:0] delay_counter = 0;
+reg strobe2s = 0;
+reg [7:0] data_fifo = 30;
+
+// 2s counter
+always_ff @(posedge clk) begin
+    if (delay_counter == CLK_FREQ * 2 - 1) begin
+        delay_counter <= 0;
+        strobe2s <= 1;
+    end else begin
+        delay_counter <= delay_counter + 1;
+        strobe2s <= 0;
+    end
+end
+
+always_ff @(posedge clk) begin
+    case (state)
+        X: begin
+            i_start <= 0;
+            wr_en <= 1;
+            wr_data <= data_fifo;
+            state <= WAIT;
+        end
+        WAIT: begin
+            i_start <= 0;
+            wr_en <= 0;
+            if (strobe2s) begin
+                state <= MESURE;
+                i_start <= 1;
+            end
+        end
+
+        MESURE: begin
+            i_start <= 0;
+            if (o_dht11_data_ready) begin
+                state <= SEND_FIFO1;
+                wr_data <= o_temp_data;
+                wr_en <= 1;
+            end
+        end
+
+        SEND_FIFO1: begin
+            wr_data <= o_hum_data;
+            wr_en <= 1;
+            state <= SEND_FIFO2;
+        end
+
+        SEND_FIFO2: begin
+            wr_en <= 0;
+            state <= WAIT;
+        end
+
+        default: state <= WAIT;
+    endcase
+end
+    
+endmodule