diff --git a/Semaine_4/UART/src/verilog/top_uart_loopback1.v b/Semaine_4/UART/src/verilog/top_uart_loopback1.v
index 8bbf7e5..378ccf8 100644
--- a/Semaine_4/UART/src/verilog/top_uart_loopback1.v
+++ b/Semaine_4/UART/src/verilog/top_uart_loopback1.v
@@ -125,8 +125,8 @@ localparam DATA_BYTE = 8'h31; // ASCII '1'
                 data_const <= DATA_BYTE;
                 tx_data <= rx_data; 
 
-                //leds[5:0] <= rx_data[5:0]; // Display received data on LEDs
-                leds[5] <= rx_received;
+                leds[5:0] <= rx_data[5:0]; // Display received data on LEDs
+            
                 delay_counter <= DELAY_CYCLES;
             end
             else if (delay_counter > 0) begin