diff --git a/Semaine_4/UART/IP/verilog/rxuartlite.v b/Semaine_4/UART/IP/verilog/rxuartlite.v
index 3584395..a527848 100644
--- a/Semaine_4/UART/IP/verilog/rxuartlite.v
+++ b/Semaine_4/UART/IP/verilog/rxuartlite.v
@@ -52,7 +52,7 @@ module rxuartlite #(
 `ifdef	FORMAL
 		parameter  [(TIMER_BITS-1):0]	CLOCKS_PER_BAUD = 16, // Necessary for formal proof
 `else
-		parameter  [(TIMER_BITS-1):0]	CLOCKS_PER_BAUD = 868,	// 115200 Baud at 100MHz
+		parameter  [(TIMER_BITS-1):0]	CLOCKS_PER_BAUD = 234,	// 115200 Baud at 100MHz
 `endif
 		localparam			TB = TIMER_BITS,
 		//
@@ -75,7 +75,7 @@ module rxuartlite #(
 		// {{{
 		input	wire		i_clk, i_reset,
 		input	wire		i_uart_rx,
-		output	reg		o_wr,
+		output	reg			o_wr,
 		output	reg	[7:0]	o_data
 		// }}}
 	);
diff --git a/Semaine_4/UART/scripts/build.bat b/Semaine_4/UART/scripts/build.bat
index ae02e91..2c9d27c 100644
--- a/Semaine_4/UART/scripts/build.bat
+++ b/Semaine_4/UART/scripts/build.bat
@@ -19,7 +19,7 @@ if not exist runs (
 )
 
 echo === Étape 1 : Synthèse avec Yosys ===
-yosys -p "read_verilog -sv src/verilog/%TOP%.v IP/verilog/other_rx.v IP/verilog/rxuartlite.v IP/verilog/other_tx.v src/verilog/uart_rx.v src/verilog/uart_tx.v; synth_gowin -top %TOP% -json %JSON_FILE%"
+yosys -p "read_verilog -sv src/verilog/%TOP%1.v IP/verilog/other_rx.v IP/verilog/rxuartlite.v IP/verilog/other_tx.v src/verilog/uart_rx.v src/verilog/uart_tx.v; synth_gowin -top %TOP% -json %JSON_FILE%"
 if errorlevel 1 goto error
 
 echo === Étape 2 : Placement & Routage avec nextpnr-himbaechel ===
diff --git a/Semaine_4/UART/src/verilog/top_uart_loopback1.v b/Semaine_4/UART/src/verilog/top_uart_loopback1.v
index 07f645c..8bbf7e5 100644
--- a/Semaine_4/UART/src/verilog/top_uart_loopback1.v
+++ b/Semaine_4/UART/src/verilog/top_uart_loopback1.v
@@ -27,6 +27,14 @@ module top_uart_loopback (
  		.rx_data(rx_data)
      );*/
 
+     rxuartlite uart_rx_inst (
+        .i_clk(clk),
+        .i_reset(1'b0),
+        .i_uart_rx(rx),
+        .o_wr(rx_received),
+        .o_data(rx_data)
+    );
+
 reg [7:0] stored_data;
 
 reg [7:0] data_const = 8'h31;
@@ -38,7 +46,7 @@ wire r;
     uart_tx uart_tx_inst (
         .clk(clk),
         .rst_p(1'b0),
-        .data(data_const),
+        .data(tx_data),
         .tx_enable(tx_enable),
         .tx_ready(tx_ready),
         .tx(tx)
@@ -115,6 +123,10 @@ localparam DATA_BYTE = 8'h31; // ASCII '1'
                 // Start new transmission
                 tx_enable <= 1'b1;
                 data_const <= DATA_BYTE;
+                tx_data <= rx_data; 
+
+                //leds[5:0] <= rx_data[5:0]; // Display received data on LEDs
+                leds[5] <= rx_received;
                 delay_counter <= DELAY_CYCLES;
             end
             else if (delay_counter > 0) begin