From aaebf22d484871784907b71daa847c6c204994f5 Mon Sep 17 00:00:00 2001
From: Gamenight77 <game.night.77176@gmail.com>
Date: Tue, 6 May 2025 09:14:59 +0200
Subject: [PATCH] Tb for fifo working fine

---
 Semaine_4/FIFO/scripts/gtkwave.bat     |  2 +-
 Semaine_4/FIFO/scripts/simulate.bat    |  2 +-
 Semaine_4/FIFO/src/verilog/fifo.v      | 10 +++-
 Semaine_4/FIFO/tests/verilog/tb_fifo.v | 79 +++++++++++++++++++++++++-
 4 files changed, 88 insertions(+), 5 deletions(-)

diff --git a/Semaine_4/FIFO/scripts/gtkwave.bat b/Semaine_4/FIFO/scripts/gtkwave.bat
index ae1cd1b..77e4564 100644
--- a/Semaine_4/FIFO/scripts/gtkwave.bat
+++ b/Semaine_4/FIFO/scripts/gtkwave.bat
@@ -1,3 +1,3 @@
 @echo off
 echo === Lancement de GTKWave ===
-gtkwave runs/uart.vcd
+gtkwave runs/fifo.vcd
diff --git a/Semaine_4/FIFO/scripts/simulate.bat b/Semaine_4/FIFO/scripts/simulate.bat
index a681db1..713979c 100644
--- a/Semaine_4/FIFO/scripts/simulate.bat
+++ b/Semaine_4/FIFO/scripts/simulate.bat
@@ -6,7 +6,7 @@ setlocal enabledelayedexpansion
 set OUT=runs/sim.vvp
 
 :: Top-level testbench module
-set TOP=tb_uart
+set TOP=tb_fifo
 
 :: Répertoires contenant des fichiers .v
 set DIRS=src/verilog tests/verilog IP/verilog
diff --git a/Semaine_4/FIFO/src/verilog/fifo.v b/Semaine_4/FIFO/src/verilog/fifo.v
index 679b0b5..4d50720 100644
--- a/Semaine_4/FIFO/src/verilog/fifo.v
+++ b/Semaine_4/FIFO/src/verilog/fifo.v
@@ -1,4 +1,4 @@
- module uart_tx #(
+ module fifo #(
 	parameter       DETPH = 16,
 	parameter       WIDTH = 8
 )(
@@ -9,7 +9,7 @@
     output wire[WIDTH-1:0]  rd_data,
 
     output wire             full,
-    output wire             empty,
+    output wire             empty
 );
 
     reg [WIDTH-1:0]         fifo[0:DETPH-1];
@@ -21,6 +21,12 @@
     assign empty = (count == 0);
     assign rd_data = fifo[rd_ptr];
 
+    initial begin
+        wr_ptr = 0;
+        rd_ptr = 0;
+        count = 0;
+    end
+
     always @(posedge clk) begin
         if (wr_en && !full) begin
             fifo[wr_ptr] <= wr_data;
diff --git a/Semaine_4/FIFO/tests/verilog/tb_fifo.v b/Semaine_4/FIFO/tests/verilog/tb_fifo.v
index f7e6aba..4bab377 100644
--- a/Semaine_4/FIFO/tests/verilog/tb_fifo.v
+++ b/Semaine_4/FIFO/tests/verilog/tb_fifo.v
@@ -4,15 +4,92 @@ module tb_fifo;
 
     reg clk = 0;
     
+    reg wr_en = 0;
+    reg rd_en = 0;
+    reg [7:0] wr_data = 0;
+    wire [7:0] rd_data;
+    wire full;
+    wire empty;
 
     always #18.5 clk = ~clk;
 
-    
+    fifo #(
+        .DETPH(16),
+        .WIDTH(8)
+    ) fifo_inst (
+        .clk(clk),
+        .wr_en(wr_en),
+        .wr_data(wr_data),
+        .rd_en(rd_en),
+        .rd_data(rd_data),
+        .full(full),
+        .empty(empty)
+    );
 
     initial begin
         $dumpfile("runs/fifo.vcd");
         $dumpvars(0, tb_fifo);
 
+        wr_en = 1;
+        wr_data = 8'hAA;
+
+        #37.0;
+
+        wr_en = 0;
+
+        #37.0;
+
+        wr_en = 1;
+        wr_data = 8'hBB;
+
+        #37.0;
+
+        wr_en = 0;
+
+        #37.0;
+
+        wr_en = 1;
+        wr_data = 8'hCC;
+
+        #37.0;
+
+        wr_en = 0;
+
+        #37.0;
+
+        $display("rd_data: %h", rd_data);
+
+        rd_en = 1;
+        $display("rd_data: %h", rd_data);
+        #37.0;
+
+        rd_en = 0;
+
+        #37.0;
+
+        rd_en = 1;
+        $display("rd_data: %h", rd_data);
+        #37.0;
+        rd_en = 0;
+
+        #37.0;
+        
+        rd_en = 1;
+        $display("rd_data: %h", rd_data);
+        #37.0;
+        rd_en = 0;
+
+        #37.0;
+
+        rd_en = 1;
+        $display("rd_data: %h", rd_data);
+        #19.0;
+        rd_en = 0;
+        
+        #37.0;
+
+
+        $finish;
         
     end