1
0
forked from tanchou/Verilog

Script pour linux structure

This commit is contained in:
2025-05-15 09:23:21 +02:00
parent 861c9869f5
commit abdc824c6d
10 changed files with 98 additions and 4 deletions

View File

@@ -1,6 +1,6 @@
@call c:\oss-cad-suite\environment.bat
@echo off
if "%1"=="sim" call scripts\simulate.bat
if "%1"=="wave" call scripts\gtkwave.bat
if "%1"=="clean" call scripts\clean.bat
if "%1"=="build" call scripts\build.bat
if "%1"=="sim" call scripts\windows\simulate.bat
if "%1"=="wave" call scripts\windows\gtkwave.bat
if "%1"=="clean" call scripts\windows\clean.bat
if "%1"=="build" call scripts\windows\build.bat