From abef18227c790ff7bf7ceee7502d487fb9692460 Mon Sep 17 00:00:00 2001 From: Gamenight77 Date: Wed, 7 May 2025 09:46:43 +0200 Subject: [PATCH] Refactor UART FIFO implementation: update top-level module and integrate RX/TX FIFO functionality --- Semaine_4/UART/scripts/build.bat | 2 +- .../UART/src/verilog/top_uart_loopback.v | 47 ++++++----- ...oopback.cst => top_uart_loopback_fifo.cst} | 0 Semaine_4/UART_FIFO/scripts/build.bat | 4 +- Semaine_4/UART_FIFO/scripts/gtkwave.bat | 2 +- Semaine_4/UART_FIFO/scripts/simulate.bat | 2 +- .../src/verilog/top_uart_loopback_fifo.v | 78 +++++++++++-------- .../UART_FIFO/src/verilog/uart_rx_fifo.v | 2 +- 8 files changed, 75 insertions(+), 62 deletions(-) rename Semaine_4/UART_FIFO/constraints/{top_uart_loopback.cst => top_uart_loopback_fifo.cst} (100%) diff --git a/Semaine_4/UART/scripts/build.bat b/Semaine_4/UART/scripts/build.bat index aed8469..f77951c 100644 --- a/Semaine_4/UART/scripts/build.bat +++ b/Semaine_4/UART/scripts/build.bat @@ -19,7 +19,7 @@ if not exist runs ( ) echo === Étape 1 : Synthèse avec Yosys === -yosys -p "read_verilog -sv src/verilog/%TOP%.v src/verilog/uart_rx.v src/verilog/uart_tx.v; synth_gowin -top %TOP% -json %JSON_FILE%" +yosys -p "read_verilog -sv src/verilog/%TOP%.v IP/verilog/other_rx.v IP/verilog/other_tx.v src/verilog/uart_rx.v src/verilog/uart_tx.v; synth_gowin -top %TOP% -json %JSON_FILE%" if errorlevel 1 goto error echo === Étape 2 : Placement & Routage avec nextpnr-himbaechel === diff --git a/Semaine_4/UART/src/verilog/top_uart_loopback.v b/Semaine_4/UART/src/verilog/top_uart_loopback.v index e7fc073..5139547 100644 --- a/Semaine_4/UART/src/verilog/top_uart_loopback.v +++ b/Semaine_4/UART/src/verilog/top_uart_loopback.v @@ -17,23 +17,23 @@ module top_uart_loopback ( end // === UART RX === - uart_rx uart_rx_inst ( + other_uart_rx uart_rx_inst ( .clk(clk), - .rst_p(1'b0), + .rst_n(1'b1), .rx_pin(rx), - .rx_received(rx_received), - .rx_enable(1'b1), + .rx_data_valid(rx_received), + .rx_data_ready(1'b1), .rx_data(rx_data) ); // === UART TX === - uart_tx uart_tx_inst ( + other_uart_tx uart_tx_inst ( .clk(clk), - .rst_p(1'b0), - .data(tx_data), - .tx_enable(tx_enable), - .tx_ready(tx_ready), - .tx(tx) + .rst_n(1'b1), + .tx_data(tx_data), + .tx_data_valid(tx_enable), + .tx_data_ready(tx_ready), + .tx_pin(tx) ); // === FSM avec délai === @@ -53,34 +53,33 @@ module top_uart_loopback ( if (rx_received && tx_ready) begin tx_data <= rx_data; state <= WAIT; - leds[0] <= 0; - leds[1] <= 1; + + leds[0] <= 0; + leds[1] <= 1; end end WAIT: begin - delay_counter <= delay_counter + 1; - - if (delay_counter == 8'd400 && tx_ready) begin - tx_enable <= 1; + if (tx_ready) begin + tx_enable <= 1; state <= SEND; end else begin - tx_enable <= 0; + tx_enable <= 0; end - - leds[0] <= 1; - leds[1] <= 0; end - SEND: begin - tx_enable <= 0; - state <= IDLE; + if (!tx_ready) begin // Attendre que la transmission commence + tx_enable <= 0; + end else if (tx_ready && tx_enable == 0) begin + state <= IDLE; // Transmission terminée, retour à l’attente + end leds[0] <= 0; - leds[1] <= 0; // Envoi terminé + leds[1] <= 0; end endcase end + endmodule \ No newline at end of file diff --git a/Semaine_4/UART_FIFO/constraints/top_uart_loopback.cst b/Semaine_4/UART_FIFO/constraints/top_uart_loopback_fifo.cst similarity index 100% rename from Semaine_4/UART_FIFO/constraints/top_uart_loopback.cst rename to Semaine_4/UART_FIFO/constraints/top_uart_loopback_fifo.cst diff --git a/Semaine_4/UART_FIFO/scripts/build.bat b/Semaine_4/UART_FIFO/scripts/build.bat index aed8469..5921792 100644 --- a/Semaine_4/UART_FIFO/scripts/build.bat +++ b/Semaine_4/UART_FIFO/scripts/build.bat @@ -7,7 +7,7 @@ cd /d %~dp0\.. rem === Config de base === set DEVICE=GW2AR-LV18QN88C8/I7 set BOARD=tangnano20k -set TOP=top_uart_loopback +set TOP=top_uart_loopback_fifo set CST_FILE=%TOP%.cst set JSON_FILE=runs/%TOP%.json set PNR_JSON=runs/pnr_%TOP%.json @@ -19,7 +19,7 @@ if not exist runs ( ) echo === Étape 1 : Synthèse avec Yosys === -yosys -p "read_verilog -sv src/verilog/%TOP%.v src/verilog/uart_rx.v src/verilog/uart_tx.v; synth_gowin -top %TOP% -json %JSON_FILE%" +yosys -p "read_verilog -sv src/verilog/%TOP%.v src/verilog/uart_rx_fifo.v src/verilog/uart_tx_fifo.v IP/verilog/fifo.v IP/verilog/uart_rx.v IP/verilog/uart_tx.v; synth_gowin -top %TOP% -json %JSON_FILE%" if errorlevel 1 goto error echo === Étape 2 : Placement & Routage avec nextpnr-himbaechel === diff --git a/Semaine_4/UART_FIFO/scripts/gtkwave.bat b/Semaine_4/UART_FIFO/scripts/gtkwave.bat index 4e7673e..7388f4c 100644 --- a/Semaine_4/UART_FIFO/scripts/gtkwave.bat +++ b/Semaine_4/UART_FIFO/scripts/gtkwave.bat @@ -1,3 +1,3 @@ @echo off echo === Lancement de GTKWave === -gtkwave runs/uart_tx_fifo.vcd +gtkwave runs/uart_rx_fifo.vcd diff --git a/Semaine_4/UART_FIFO/scripts/simulate.bat b/Semaine_4/UART_FIFO/scripts/simulate.bat index 54604a3..439cda3 100644 --- a/Semaine_4/UART_FIFO/scripts/simulate.bat +++ b/Semaine_4/UART_FIFO/scripts/simulate.bat @@ -6,7 +6,7 @@ setlocal enabledelayedexpansion set OUT=runs/sim.vvp :: Top-level testbench module -set TOP=tb_uart_tx_fifo +set TOP=tb_uart_rx_fifo :: Répertoires contenant des fichiers .v set DIRS=src/verilog tests/verilog IP/verilog diff --git a/Semaine_4/UART_FIFO/src/verilog/top_uart_loopback_fifo.v b/Semaine_4/UART_FIFO/src/verilog/top_uart_loopback_fifo.v index a83d995..6a24836 100644 --- a/Semaine_4/UART_FIFO/src/verilog/top_uart_loopback_fifo.v +++ b/Semaine_4/UART_FIFO/src/verilog/top_uart_loopback_fifo.v @@ -1,65 +1,79 @@ -module top_uart_loopback ( +module top_uart_loopback_fifo ( input wire clk, // 27 MHz input wire rx, output wire tx, output reg [5:0] leds ); - wire rx_received; - wire [7:0] rx_data; - reg [7:0] tx_data; - reg tx_enable; - wire tx_ready; + // === UART TX === + reg [7:0] wr_data; + reg wr_en; + wire tx_fifo_full; + + wire [7:0] rd_data; + reg rd_en; + wire data_available; initial begin - leds = 6'b000000; // Initialiser les LEDs à 0 + leds = 6'b111111; // Initialiser les LEDs à 0 end // === UART RX === - uart_rx uart_rx_inst ( + uart_rx_fifo uart_rx_inst ( .clk(clk), - .rst_p(1'b0), .rx_pin(rx), - .rx_received(rx_received), - .rx_enable(1'b1), - .rx_data(rx_data) + .rd_data(rd_data), + .rd_en(rd_en), + .data_available(data_available) ); // === UART TX === - uart_tx uart_tx_inst ( + uart_tx_fifo uart_tx_inst ( .clk(clk), - .rst_p(1'b0), - .data(tx_data), - .tx_enable(tx_enable), - .tx_ready(tx_ready), - .tx(tx) + .wr_en(wr_en), + .wr_data(wr_data), + .fifo_full(tx_fifo_full), + .tx_pin(tx) ); // === FSM pour déclencher la transmission === - localparam IDLE = 0, SEND = 1; - reg state = IDLE; + localparam IDLE = 0, PREP_READ = 1, READ = 2, WRITE = 3; + reg [1:0] state = IDLE; always @(posedge clk) begin + // Par défaut + wr_en <= 0; + rd_en <= 0; + + // Debug visuel leds[5] <= rx; + leds[4] <= tx; + leds[3] <= data_available; + leds[2] <= ~fifo_full; + case (state) IDLE: begin - tx_enable <= 0; - if (rx_received && tx_ready) begin - tx_data <= rx_data; - tx_enable <= 1; - state <= SEND; - leds[0] <= 1; - leds[5:1] <= 0; + if (data_available && !fifo_full) begin + rd_en <= 1; // Mettre rd_en à 1 maintenant + state <= PREP_READ; end end - SEND: begin - tx_enable <= 0; - state <= IDLE; + PREP_READ: begin + rd_en <= 1; + state <= READ; + end - leds[0] <= 0; // LED 0 allumée pour indiquer la réception - leds[1] <= 1; // LED 1 éteinte pour indiquer l'attente de transmission + READ: begin + rd_en <= 0; + wr_data <= rd_data; + state <= WRITE; + end + + WRITE: begin + wr_en <= 1; + state <= IDLE; end endcase end diff --git a/Semaine_4/UART_FIFO/src/verilog/uart_rx_fifo.v b/Semaine_4/UART_FIFO/src/verilog/uart_rx_fifo.v index 06c1b1f..4d56109 100644 --- a/Semaine_4/UART_FIFO/src/verilog/uart_rx_fifo.v +++ b/Semaine_4/UART_FIFO/src/verilog/uart_rx_fifo.v @@ -5,7 +5,7 @@ module uart_rx_fifo #( )( input clk, input rd_en, - output reg [7:0] rd_data, + output reg [7:0] rd_data, input rx_pin, output data_available );