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Refactor ultrasonic modules and testbench for improved functionality and clarity

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This commit is contained in:
Louis TANCHOU
2025-05-20 14:24:41 +02:00
parent 436edae734
commit b3e646d854
8 changed files with 115 additions and 83 deletions
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6
Semaine_6/UART_ULTRASON_COMMANDS/src/verilog/top_uart_ultrason_command.v
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@@ -64,21 +64,25 @@ module top_uart_ultrason_command (
always @(posedge clk) begin
if (data_available) begin
command <= rd_data[1:0];
leds <= rd_data[7:2];
end else begin
command <= 0;
end
leds <= {~command, ~mesure_state};
end
always @(posedge clk) begin // Mesure state machine
case (mesure_state)
IDLE: begin
if (command == 2'd1 && data_available) begin
mesure_state <= ONESTART;
rd_en <= 1;
end else if (command == 2'd2 && data_available) begin
mesure_state <= CONTINUOUSSTART;
rd_en <= 1;
end else if (command == 2'd3 && data_available) begin
mesure_state <= IDLE;
rd_en <= 1;
end else begin
mesure_state <= IDLE;
rd_en <= 0;