verlan/Verilog_Louis
1
0
Fork 0
forked from tanchou/Verilog
Code Pull Requests Activity

Refactor ultrasonic modules and testbench for improved functionality and clarity

Browse Source
This commit is contained in:
Louis TANCHOU
2025-05-20 14:24:41 +02:00
parent 436edae734
commit b3e646d854
8 changed files with 115 additions and 83 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
Semaine_6/UART_ULTRASON_COMMANDS/tests/Python/ultrason_command.py
View File

@@ -3,7 +3,7 @@ import time
import struct
# === Paramètres de communication ===
SERIAL_PORT = "COM6" # Modifie selon ton système, ex. "/dev/ttyUSB0" sur Linux
SERIAL_PORT = "COM10" # Modifie selon ton système, ex. "/dev/ttyUSB0" sur Linux
BAUDRATE = 115200 # Change si différent
TIMEOUT = 2 # secondes