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Refactor ultrasonic modules and testbench for improved functionality and clarity

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This commit is contained in:
Louis TANCHOU
2025-05-20 14:24:41 +02:00
parent 436edae734
commit b3e646d854
8 changed files with 115 additions and 83 deletions
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9
Semaine_6/ULTRASON/src/verilog/hc_sr04_model.v
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@@ -13,7 +13,8 @@ module hc_sr04_model #(
// Timing constants based on CLK_FREQ_MHZ
localparam CLK_PERIOD_NS = 1000 / CLK_FREQ_MHZ; // Clock period in ns
localparam TRIGGER_MIN_CYCLES = (10_000 / CLK_PERIOD_NS); // 10us minimum trigger pulse
localparam CYCLE_TIME_CYCLES = (60_000_000 / CLK_PERIOD_NS); // 60ms cycle time
// localparam CYCLE_TIME_CYCLES = (60_000_000 / CLK_PERIOD_NS); // 60ms cycle time
localparam CYCLE_TIME_CYCLES = (60 / CLK_PERIOD_NS); // 60ms cycle time
localparam ECHO_DELAY_CYCLES = (1000 / CLK_PERIOD_NS); // 1us delay before echo (sensor processing)
// State machine states
@@ -34,7 +35,7 @@ module hc_sr04_model #(
// Speed of sound: 343 m/s = 0.0343 cm/us
// Echo duration (us) = 2 * distance (cm) / 0.0343 (cm/us)
// Convert to clock cycles: duration (us) * 1000 / CLK_PERIOD_NS
wire [31:0] echo_duration_us = (2 * random_distance * 1000) / 343; // Echo time in us
wire [31:0] echo_duration_us = (2 * random_distance * 10_000) / 343; // Echo time in us
wire [31:0] calculated_echo_cycles = (echo_duration_us * 1000) / CLK_PERIOD_NS; // Echo time in cycles
// Bidirectional pin control: drive sensor_pin only during echo pulse
@@ -57,7 +58,9 @@ module hc_sr04_model #(
CHECK_TRIGGER: begin
counter <= counter + 1;
if (!sensor_pin) begin // Trigger pulse ended
if (sensor_pin) begin // Trigger pulse ended
end
else begin
if (counter >= TRIGGER_MIN_CYCLES) begin
$display("HC-SR04: Random distance = %0d cm at time %0t", random_distance, $time);
echo_cycles <= calculated_echo_cycles; // Sample echo duration

6
Semaine_6/ULTRASON/src/verilog/ultrason_driver.v
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@@ -32,7 +32,8 @@ module ultrason_driver #(
reg [2:0] state = IDLE;
localparam integer TRIG_PULSE_CYCLES = CLK_FREQ / 100_000; // 10us pulse
localparam integer TRIG_PULSE_CYCLES = CLK_FREQ / 100_000 + 5; // 10us pulse
// localparam integer DIST_DIVISOR = ((CLK_FREQ / 100) / 343) * 2; // pour conversion us -> cm
localparam integer DIST_DIVISOR = (58 * CLK_FREQ) / 1_000_000; // pour conversion us -> cm
localparam integer MAX_CM = 350;
localparam integer TIMEOUT_CYCLES = (MAX_CM * 58 * CLK_FREQ) / 1000000;
@@ -58,6 +59,9 @@ module ultrason_driver #(
sig_out <= 0;
sig_dir <= 0;
distance <= 0;
echo_counter <= 0;
distance_counter <= 0;
trig_counter <= 0;
if (start) begin
state <= TRIG_HIGH;

8
Semaine_6/ULTRASON/src/verilog/ultrasonic_fpga.v
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@@ -32,7 +32,8 @@ module ultrasonic_fpga #(
reg [2:0] state = IDLE;
localparam integer TRIG_PULSE_CYCLES = CLK_FREQ / 100_000; // 10us pulse
localparam integer TRIG_PULSE_CYCLES = CLK_FREQ / 100_000 + 5; // 10us pulse
// localparam integer DIST_DIVISOR = ((CLK_FREQ / 100) / 343) * 2; // pour conversion us -> cm
localparam integer DIST_DIVISOR = (58 * CLK_FREQ) / 1_000_000; // pour conversion us -> cm
localparam integer MAX_CM = 350;
localparam integer TIMEOUT_CYCLES = (MAX_CM * 58 * CLK_FREQ) / 1000000;
@@ -58,6 +59,10 @@ module ultrasonic_fpga #(
sig_out <= 0;
sig_dir <= 0;
distance <= 0;
echo_counter <= 0;
distance_counter <= 0;
trig_counter <= 0;
if (start) begin
state <= TRIG_HIGH;
trig_counter <= 0;
@@ -68,6 +73,7 @@ module ultrasonic_fpga #(
TRIG_HIGH: begin
sig_out <= 1;
sig_dir <= 1;
if (trig_counter < TRIG_PULSE_CYCLES) begin
trig_counter <= trig_counter + 1;
end else begin