verlan/Verilog_Louis
1
0
Fork 0
forked from tanchou/Verilog
Code Pull Requests Activity

Refactor ultrasonic modules and testbench for improved functionality and clarity

Browse Source
This commit is contained in:
Louis TANCHOU
2025-05-20 14:24:41 +02:00
parent 436edae734
commit b3e646d854
8 changed files with 115 additions and 83 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
Semaine_6/ULTRASON/src/verilog/ultrason_driver.v
View File

@@ -32,7 +32,8 @@ module ultrason_driver #(
reg [2:0] state = IDLE;
localparam integer TRIG_PULSE_CYCLES = CLK_FREQ / 100_000; // 10us pulse
localparam integer TRIG_PULSE_CYCLES = CLK_FREQ / 100_000 + 5; // 10us pulse
// localparam integer DIST_DIVISOR = ((CLK_FREQ / 100) / 343) * 2; // pour conversion us -> cm
localparam integer DIST_DIVISOR = (58 * CLK_FREQ) / 1_000_000; // pour conversion us -> cm
localparam integer MAX_CM = 350;
localparam integer TIMEOUT_CYCLES = (MAX_CM * 58 * CLK_FREQ) / 1000000;
@@ -58,6 +59,9 @@ module ultrason_driver #(
sig_out <= 0;
sig_dir <= 0;
distance <= 0;
echo_counter <= 0;
distance_counter <= 0;
trig_counter <= 0;
if (start) begin
state <= TRIG_HIGH;