diff --git a/Semaine_4/FIFO/src/verilog/fifo.v b/Semaine_4/FIFO/src/verilog/fifo.v
index 031be59..6135d3b 100644
--- a/Semaine_4/FIFO/src/verilog/fifo.v
+++ b/Semaine_4/FIFO/src/verilog/fifo.v
@@ -34,8 +34,8 @@
end
if (rd_en && !empty) begin // OUT
- rd_ptr <= (rd_ptr + 1) % SIZE;
rd_data <= fifo[rd_ptr];
+ rd_ptr <= (rd_ptr + 1) % SIZE;
count <= count - 1;
end
end
diff --git a/Semaine_4/UART_FIFO/src/verilog/uart_rx_fifo.v b/Semaine_4/UART_FIFO/src/verilog/uart_rx_fifo.v
index c9e8625..d521fde 100644
--- a/Semaine_4/UART_FIFO/src/verilog/uart_rx_fifo.v
+++ b/Semaine_4/UART_FIFO/src/verilog/uart_rx_fifo.v
@@ -5,7 +5,7 @@ module uart_rx_fifo #(
)(
input clk,
input rd_en,
- output reg [7:0] rd_data,
+ output wire [7:0] rd_data,
input rx_pin,
output data_available
);
@@ -18,7 +18,6 @@ module uart_rx_fifo #(
reg wr_en;
wire fifo_empty;
wire fifo_full;
- wire [7:0] fifo_rd_data;
// UART Receiver instance
rxuartlite uart_rx_inst (
@@ -38,20 +37,13 @@ module uart_rx_fifo #(
.wr_en(wr_en),
.wr_data(rx_data),
.rd_en(rd_en),
- .rd_data(fifo_rd_data),
+ .rd_data(rd_data),
.empty(fifo_empty),
.full(fifo_full)
);
assign data_available = ~fifo_empty;
- // Enregistrement explicite des données lues pour stabilité
- always @(posedge clk) begin
- if (rd_en && !fifo_empty) begin
- rd_data <= fifo_rd_data;
- end
- end
-
// Écriture dans la FIFO uniquement si donnée reçue ET FIFO pas pleine
always @(posedge clk) begin
if (rx_received && !fifo_full) begin
diff --git a/Semaine_5/UART_ULTRASON_COMMANDS/IP/verilog/fifo.v b/Semaine_5/UART_ULTRASON_COMMANDS/IP/verilog/fifo.v
index 031be59..6135d3b 100644
--- a/Semaine_5/UART_ULTRASON_COMMANDS/IP/verilog/fifo.v
+++ b/Semaine_5/UART_ULTRASON_COMMANDS/IP/verilog/fifo.v
@@ -34,8 +34,8 @@
end
if (rd_en && !empty) begin // OUT
- rd_ptr <= (rd_ptr + 1) % SIZE;
rd_data <= fifo[rd_ptr];
+ rd_ptr <= (rd_ptr + 1) % SIZE;
count <= count - 1;
end
end
diff --git a/Semaine_5/UART_ULTRASON_COMMANDS/IP/verilog/uart_rx_fifo.v b/Semaine_5/UART_ULTRASON_COMMANDS/IP/verilog/uart_rx_fifo.v
index c9e8625..d521fde 100644
--- a/Semaine_5/UART_ULTRASON_COMMANDS/IP/verilog/uart_rx_fifo.v
+++ b/Semaine_5/UART_ULTRASON_COMMANDS/IP/verilog/uart_rx_fifo.v
@@ -5,7 +5,7 @@ module uart_rx_fifo #(
)(
input clk,
input rd_en,
- output reg [7:0] rd_data,
+ output wire [7:0] rd_data,
input rx_pin,
output data_available
);
@@ -18,7 +18,6 @@ module uart_rx_fifo #(
reg wr_en;
wire fifo_empty;
wire fifo_full;
- wire [7:0] fifo_rd_data;
// UART Receiver instance
rxuartlite uart_rx_inst (
@@ -38,20 +37,13 @@ module uart_rx_fifo #(
.wr_en(wr_en),
.wr_data(rx_data),
.rd_en(rd_en),
- .rd_data(fifo_rd_data),
+ .rd_data(rd_data),
.empty(fifo_empty),
.full(fifo_full)
);
assign data_available = ~fifo_empty;
- // Enregistrement explicite des données lues pour stabilité
- always @(posedge clk) begin
- if (rd_en && !fifo_empty) begin
- rd_data <= fifo_rd_data;
- end
- end
-
// Écriture dans la FIFO uniquement si donnée reçue ET FIFO pas pleine
always @(posedge clk) begin
if (rx_received && !fifo_full) begin
diff --git a/Semaine_5/UART_ULTRASON_COMMANDS/IP/verilog/ultrasonic_fpga.v b/Semaine_5/UART_ULTRASON_COMMANDS/IP/verilog/ultrasonic_fpga.v
index ca885d7..c11d19e 100644
--- a/Semaine_5/UART_ULTRASON_COMMANDS/IP/verilog/ultrasonic_fpga.v
+++ b/Semaine_5/UART_ULTRASON_COMMANDS/IP/verilog/ultrasonic_fpga.v
@@ -54,7 +54,7 @@ module ultrasonic_fpga #(
case (state)
IDLE: begin
- done <= 1;
+ done <= 0;
sig_out <= 0;
sig_dir <= 0;
distance <= 0;
diff --git a/Semaine_5/UART_ULTRASON_COMMANDS/src/verilog/top_uart_ultrason_command.v b/Semaine_5/UART_ULTRASON_COMMANDS/src/verilog/top_uart_ultrason_command.v
index 965c894..b397089 100644
--- a/Semaine_5/UART_ULTRASON_COMMANDS/src/verilog/top_uart_ultrason_command.v
+++ b/Semaine_5/UART_ULTRASON_COMMANDS/src/verilog/top_uart_ultrason_command.v
@@ -52,7 +52,7 @@ module top_uart_ultrason_command (
);
// === FSM ===
- localparam IDLE = 0, READ = 1;
+ localparam IDLE = 0, READ = 1, DECODE = 2;
localparam STOP = 3, ONE = 1, CONTINUOUS = 2;
reg [1:0] rx_state = IDLE;
@@ -84,6 +84,11 @@ module top_uart_ultrason_command (
READ: begin
leds [5] <= 1;
+ rd_en <= 1'b1;
+ rx_state <= DECODE;
+ end
+
+ DECODE: begin
case (rd_data)
8'h01: begin // Start mesure one mesure
start <= 1;
@@ -103,7 +108,7 @@ module top_uart_ultrason_command (
rx_state <= IDLE;
end
- default: begin
+ default: begin
mesure <= STOP;
rx_state <= IDLE;
end
@@ -116,7 +121,9 @@ module top_uart_ultrason_command (
// Mesure block
always @(posedge clk) begin
leds <= mesure[1:0];
+
case (tx_state)
+
MESURE: begin
case (mesure)
STOP: begin // Stop mesure
@@ -128,9 +135,10 @@ module top_uart_ultrason_command (
if (done) begin
tx_state <= SEND_LOW;
wr_en <= 1;
+ mesure <= STOP;
end else begin
tx_state <= MESURE;
- mesure <= STOP;
+ mesure <= ONE;
end
end
@@ -152,7 +160,7 @@ module top_uart_ultrason_command (
SEND_LOW: begin
wr_en <= 1;
wr_data <= distance[7:0]; // Octet LSB
- tx_state <= SEND_HIGH;
+ tx_state <= WAIT;
end
SEND_HIGH: begin
diff --git a/Semaine_5/UART_ULTRASON_COMMANDS/tests/Python/.idea/.gitignore b/Semaine_5/UART_ULTRASON_COMMANDS/tests/Python/.idea/.gitignore
new file mode 100644
index 0000000..13566b8
--- /dev/null
+++ b/Semaine_5/UART_ULTRASON_COMMANDS/tests/Python/.idea/.gitignore
@@ -0,0 +1,8 @@
+# Default ignored files
+/shelf/
+/workspace.xml
+# Editor-based HTTP Client requests
+/httpRequests/
+# Datasource local storage ignored files
+/dataSources/
+/dataSources.local.xml
diff --git a/Semaine_5/UART_ULTRASON_COMMANDS/tests/Python/.idea/Python.iml b/Semaine_5/UART_ULTRASON_COMMANDS/tests/Python/.idea/Python.iml
new file mode 100644
index 0000000..07abf20
--- /dev/null
+++ b/Semaine_5/UART_ULTRASON_COMMANDS/tests/Python/.idea/Python.iml
@@ -0,0 +1,12 @@
+
+
+
+
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/Semaine_5/UART_ULTRASON_COMMANDS/tests/Python/.idea/inspectionProfiles/profiles_settings.xml b/Semaine_5/UART_ULTRASON_COMMANDS/tests/Python/.idea/inspectionProfiles/profiles_settings.xml
new file mode 100644
index 0000000..105ce2d
--- /dev/null
+++ b/Semaine_5/UART_ULTRASON_COMMANDS/tests/Python/.idea/inspectionProfiles/profiles_settings.xml
@@ -0,0 +1,6 @@
+
+
+
+
+
+
\ No newline at end of file
diff --git a/Semaine_5/UART_ULTRASON_COMMANDS/tests/Python/.idea/misc.xml b/Semaine_5/UART_ULTRASON_COMMANDS/tests/Python/.idea/misc.xml
new file mode 100644
index 0000000..060d2c5
--- /dev/null
+++ b/Semaine_5/UART_ULTRASON_COMMANDS/tests/Python/.idea/misc.xml
@@ -0,0 +1,4 @@
+
+
+
+
\ No newline at end of file
diff --git a/Semaine_5/UART_ULTRASON_COMMANDS/tests/Python/.idea/modules.xml b/Semaine_5/UART_ULTRASON_COMMANDS/tests/Python/.idea/modules.xml
new file mode 100644
index 0000000..3097039
--- /dev/null
+++ b/Semaine_5/UART_ULTRASON_COMMANDS/tests/Python/.idea/modules.xml
@@ -0,0 +1,8 @@
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/Semaine_5/UART_ULTRASON_COMMANDS/tests/Python/.idea/vcs.xml b/Semaine_5/UART_ULTRASON_COMMANDS/tests/Python/.idea/vcs.xml
new file mode 100644
index 0000000..4fce1d8
--- /dev/null
+++ b/Semaine_5/UART_ULTRASON_COMMANDS/tests/Python/.idea/vcs.xml
@@ -0,0 +1,6 @@
+
+
+
+
+
+
\ No newline at end of file
diff --git a/Semaine_5/UART_ULTRASON_COMMANDS/tests/verilog/tb_ultrason_commands.v b/Semaine_5/UART_ULTRASON_COMMANDS/tests/verilog/tb_ultrason_commands.v
index bd6b336..5932631 100644
--- a/Semaine_5/UART_ULTRASON_COMMANDS/tests/verilog/tb_ultrason_commands.v
+++ b/Semaine_5/UART_ULTRASON_COMMANDS/tests/verilog/tb_ultrason_commands.v
@@ -13,7 +13,7 @@ module tb_ultrason_commands;
wire tx_ready;
reg [7:0] data_in = 8'h00;
wire [7:0] data_out;
- wire rx_received;
+ wire data_available;
reg rd_en = 0; // Lecture FIFO
@@ -42,13 +42,13 @@ module tb_ultrason_commands;
.BAUD_RATE(BAUD_RATE)
) uart_rx_fifo_inst (
.clk(clk),
- .rx_pin(rx), // on observe la sortie du DUT
+ .rx_pin(tx),
.rd_en(rd_en),
.rd_data(data_out),
- .data_available(rx_received)
+ .data_available(data_available)
);
- // === TX pour injecter une commande UART vers le DUT ===
+ // === TX pour injecter une commande UART ===
uart_tx #(
.CLK_FREQ(CLK_FREQ),
.BAUD_RATE(BAUD_RATE)
@@ -57,7 +57,7 @@ module tb_ultrason_commands;
.tx_enable(tx_enable),
.tx_ready(tx_ready),
.data(data_in),
- .tx(tx), // va dans le DUT
+ .tx(rx),
.rst_p(1'b0)
);
@@ -70,6 +70,7 @@ module tb_ultrason_commands;
// Attendre que le TX soit prêt
wait(tx_ready);
+ $display(">> TX ready");
#100;
// Envoyer la commande "ONE" (1)
@@ -77,19 +78,25 @@ module tb_ultrason_commands;
tx_enable <= 1;
#20;
tx_enable <= 0;
+ $display(">> Command sent: %d", data_in);
// Lire 2 octets de réponse : LSB et MSB de la distance
repeat (2) begin
- wait(rx_received);
+ wait(data_available);
+
+ //D
#10; // Laisse le temps de valider le drapeau
rd_en <= 1; // Lecture de la FIFO
- #20;
+ #30;
rd_en <= 0;
+
+
+ #200;
$display(">> Distance octet: %d", data_out);
end
$display("==== End UART Ultrasonic Test ====");
- #1000;
+ #10000;
$stop;
end