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Refactor ultrasonic FPGA module: add echo_div_counter and distance_counter for improved distance measurement logic

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Gamenight77
2025-04-25 09:23:33 +02:00
parent d8708d1bd5
commit bc7518a231
1 changed files with 14 additions and 4 deletions
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16
Semaine_1/Capteur_recule_bidirectionel/Ultrasonic/ultrasonic_fpga.v
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@@ -9,6 +9,9 @@ module ultrasonic_fpga #(
); );
reg [15:0] trig_counter; reg [15:0] trig_counter;
reg [31:0] echo_counter; reg [31:0] echo_counter;
reg [31:0] echo_div_counter;
reg [15:0] distance_counter;
reg sig_out; reg sig_out;
reg sig_dir; // 1: output, 0: input reg sig_dir; // 1: output, 0: input
@@ -26,7 +29,6 @@ module ultrasonic_fpga #(
DONE = 3'd5, DONE = 3'd5,
WAIT_NEXT = 3'd6; WAIT_NEXT = 3'd6;
localparam integer TRIG_PULSE_CYCLES = CLK_FREQ / 100_000; // 10us pulse localparam integer TRIG_PULSE_CYCLES = CLK_FREQ / 100_000; // 10us pulse
localparam integer DIST_DIVISOR = (58 * CLK_FREQ) / 1_000_000; // pour conversion us -> cm localparam integer DIST_DIVISOR = (58 * CLK_FREQ) / 1_000_000; // pour conversion us -> cm
localparam integer MAX_CM = 350; localparam integer MAX_CM = 350;
@@ -36,7 +38,6 @@ module ultrasonic_fpga #(
reg [31:0] wait_counter; reg [31:0] wait_counter;
always @(posedge clk) begin // FSM always @(posedge clk) begin // FSM
case (state) case (state)
@@ -87,8 +88,17 @@ module ultrasonic_fpga #(
distance <= 0; distance <= 0;
state <= DONE; state <= DONE;
end end
end else begin //Comptage par cycle de dist diviseur
echo_counter <= echo_counter + 1;
if (echo_div_counter >= DIST_DIVISOR - 1) begin
echo_div_counter <= 0;
distance_counter <= distance_counter + 1;
end else begin end else begin
distance <= (echo_counter * 1000) / DIST_DIVISOR; echo_div_counter <= echo_div_counter + 1;
end
distance <= distance_counter;
state <= DONE; state <= DONE;
end end
end end