verlan/Verilog_Louis
1
0
Fork 0
forked from tanchou/Verilog
Code Pull Requests Activity

Implement distance measurement and display modules: add ultrasonic sensor, FPGA logic, LED display, and WS2812 driver for enhanced distance visualization

Browse Source
This commit is contained in:
Gamenight77
2025-04-25 10:21:18 +02:00
parent eecf17f45d
commit c6d33d278e
10 changed files with 454 additions and 14 deletions
Download Patch File Download Diff File Expand all files Collapse all files

79
Semaine_1/Capteur_recule_bidirectionel/Ultrasonic/ultrasonic_sensor.v
View File

@@ -1,79 +0,0 @@
module ultrasonic_sensor(// Simulation of an ultrasonic sensor
input wire clk,
inout wire signal, // Signal from the ultrasonic sensor
);
reg [2:0] state, next_state;
reg sig_dir; // 1: output, 0: input
reg [15:0] trig_counter; // Counter for the trigger pulse
reg [31:0] echo_counter; // Echo signal
reg valid_trig; // Valid trigger signal
reg echo_sended; // Flag to indicate if echo has been sent
localparam S_WAIT_TRIG = 3'd0,
S_MEASURE_TRIG = 3'd1,
S_SEND_ECHO = 3'd2,
localparam integer TRIG_PULSE_CYCLES = CLK_FREQ / 100_000; // 10us pulse
always @(*) begin
case (state)
S_WAIT_TRIG: begin
sig_dir = 0;
if (signal == 1) begin
next_state = S_MEASURE_TRIG;
end else begin
next_state = S_WAIT_TRIG;
end
end
S_MEASURE_TRIG: begin
sig_dir = 0;
if (valid_trig)begin
next_state = S_SEND_ECHO;
end
end
S_SEND_ECHO: begin
sig_dir = 1; // Mettre en sortie
if (echo_sended) begin
echo_sended = 0; // Reset flag
next_state = S_WAIT_TRIG;
end else begin
signal = 1; // Send echo signal
#5800; // Wait for 5800ns (≈ 100 cycles @ 27MHz => ≈ 100 cm aller-retour)
signal = 0; // Stop sending echo signal
echo_sended = 1; // Set flag to indicate echo has been sent
end
next_state = S_WAIT_TRIG;
end
default: begin
sig_dir = 0;
next_state = S_WAIT_TRIG;
end
endcase
end
always @(posedge clk) begin
state <= next_state;
if (~sig_dir) begin
signal <= 1'bz;
end
end
always @(posedge clk) begin
if (state == S_MEASURE_TRIG) begin
if (signal == 1) begin
trig_counter <= trig_counter + 1;
end else begin
if (trig_counter >= TRIG_PULSE_CYCLES-2 && trig_counter <= TRIG_PULSE_CYCLES+2) begin
valid_trig <= 1;
end else begin
valid_trig <= 0;
end
end
end
end
endmodule