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Implement distance measurement and display modules: add ultrasonic sensor, FPGA logic, LED display, and WS2812 driver for enhanced distance visualization

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Gamenight77
2025-04-25 10:21:18 +02:00
parent eecf17f45d
commit c6d33d278e
10 changed files with 454 additions and 14 deletions
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59
Semaine_2/Capteur_recule_bidirectionel_V2/Ultrasonic/tb_ultrasonic_fpga.v Normal file
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`timescale 1ns/1ps
module tb_ultrasonic_fpga;
reg clk = 0;
reg rst = 1;
reg start = 0;
wire sig;
wire [8:0] distance;
time t_start, t_end;
// Clock 27MHz => periode = 37ns
always #18 clk = ~clk;
ultrasonic_fpga uut (
.clk(clk),
.rst(rst),
.start(start),
.sig(sig),
.distance(distance)
);
ultrasonic_sensor sensor (
.clk(clk),
.signal(sig)
);
initial begin
$dumpfile("ultrasonic.vcd");
$dumpvars(0, tb_ultrasonic_fpga);
// Reset
#100;
rst = 0;
// Start
#100;
start = 1;
#40;
start = 0;
// Attendre que la distance soit mesurée
wait (distance > 0);
#10; // petite marge pour stabiliser
$display("Distance mesurée: %d cm", distance);
// Affiche la distance
if (distance > 0) begin
$display("Distance measured: %d cm", distance);
end else begin
$display("No distance measured.");
end
$finish;
end
endmodule

127
Semaine_2/Capteur_recule_bidirectionel_V2/Ultrasonic/ultrasonic_fpga.v Normal file
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module ultrasonic_fpga #(
parameter integer CLK_FREQ = 27_000_000 // Fréquence d'horloge en Hz
)(
input wire clk,
input wire start,
inout wire sig, // Broche bidirectionnelle vers le capteur
output reg [15:0] distance, // Distance mesurée en cm
output reg [2:0] state = IDLE
);
reg [15:0] trig_counter;
reg [31:0] echo_counter;
reg [31:0] echo_div_counter;
reg [15:0] distance_counter;
reg sig_out;
reg sig_dir; // 1: output, 0: input
assign sig = sig_dir ? sig_out : 1'bz; // bz pour dire que le fpga laisse le fils libre et n'oblige pas de valeur
reg sig_int, sig_ok;
always_ff(@posedge clk) {sig_ok, sig_int} = {sig_int, sig};
localparam IDLE = 3'd0,
TRIG_HIGH = 3'd1,
TRIG_LOW = 3'd2,
WAIT_ECHO = 3'd3,
MEASURE_ECHO = 3'd4,
DONE = 3'd5,
WAIT_NEXT = 3'd6;
localparam integer TRIG_PULSE_CYCLES = CLK_FREQ / 100_000; // 10us pulse
localparam integer DIST_DIVISOR = (58 * CLK_FREQ) / 1_000_000; // pour conversion us -> cm
localparam integer MAX_CM = 350;
localparam integer TIMEOUT_CYCLES = (MAX_CM * 58 * CLK_FREQ) / 1_000_000;
localparam WAIT_NEXT_CYCLES = (CLK_FREQ / 1000) * 100; // 60 ms
reg [31:0] wait_counter;
always @(posedge clk) begin // FSM
case (state)
IDLE: begin
sig_out <= 0;
sig_dir <= 1;
distance <= 0;
if (start) begin
state <= TRIG_HIGH;
trig_counter <= 0;
end
end
TRIG_HIGH: begin
sig_out <= 1;
sig_dir <= 1;
if (trig_counter < TRIG_PULSE_CYCLES) begin
trig_counter <= trig_counter + 1;
end else begin
trig_counter <= 0;
state <= TRIG_LOW;
end
end
TRIG_LOW: begin
sig_out <= 0;
sig_dir <= 0; // Mettre en entrée
state <= WAIT_ECHO;
end
WAIT_ECHO: begin
if (sig_ok) begin
echo_counter <= 0;
state <= MEASURE_ECHO;
end else if (echo_counter >= TIMEOUT_CYCLES) begin
distance <= 0;
state <= DONE;
end else begin
echo_counter <= echo_counter + 1;
end
end
MEASURE_ECHO: begin
if (sig_ok) begin
if (echo_counter < TIMEOUT_CYCLES) begin
echo_counter <= echo_counter + 1;
end else begin
distance <= 0;
state <= DONE;
end
end else begin //Comptage par cycle de dist diviseur
echo_counter <= echo_counter + 1;
if (echo_div_counter >= DIST_DIVISOR - 1) begin
echo_div_counter <= 0;
distance_counter <= distance_counter + 1;
end else begin
echo_div_counter <= echo_div_counter + 1;
end
distance <= distance_counter;
state <= DONE;
end
end
DONE: begin
if (start) begin
wait_counter <= 0;
state <= WAIT_NEXT;
end else begin
state <= IDLE;
end
end
WAIT_NEXT: begin
wait_counter <= wait_counter + 1;
if (wait_counter >= WAIT_NEXT_CYCLES) begin
state <= TRIG_HIGH;
end
end
endcase
end
endmodule

97
Semaine_2/Capteur_recule_bidirectionel_V2/Ultrasonic/ultrasonic_sensor.v Normal file
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module ultrasonic_sensor( // Simulation of an ultrasonic sensor
input wire clk,
inout wire signal, // Signal from the ultrasonic sensor
);
parameter integer CLK_FREQ = 27_000_000;
reg [2:0] state, next_state;
reg sig_dir; // 1: output, 0: input
reg [15:0] trig_counter; // Counter for the trigger pulse
reg [31:0] echo_counter; // Echo signal
reg valid_trig; // Valid trigger signal
reg echo_sended; // Flag to indicate if echo has been sent
reg signal_out;
assign signal = sig_dir ? signal_out : 1'bz; // Assign the signal to the output if sig_dir is high, otherwise set it to high impedance
localparam S_WAIT_TRIG = 3'd0,
S_MEASURE_TRIG = 3'd1,
S_SEND_ECHO = 3'd2;
localparam integer TRIG_PULSE_CYCLES = CLK_FREQ / 100_000; // 10us pulse
always @(*) begin
case (state)
S_WAIT_TRIG: begin
sig_dir = 0;
if (signal == 1) begin
next_state = S_MEASURE_TRIG;
end else begin
next_state = S_WAIT_TRIG;
end
end
S_MEASURE_TRIG: begin
sig_dir = 0;
if (valid_trig)begin
next_state = S_SEND_ECHO;
end
end
S_SEND_ECHO: begin
sig_dir = 1; // Mettre en sortie
if (echo_sended) begin
echo_sended = 0; // Reset flag
next_state = S_WAIT_TRIG;
end else begin
next_state = S_SEND_ECHO;
end
end
default: begin
sig_dir = 0;
next_state = S_WAIT_TRIG;
end
endcase
end
always @(posedge clk) begin
state <= next_state;
if (~sig_dir) begin
signal <= 1'bz;
end
end
always @(posedge clk) begin
if (state == S_MEASURE_TRIG) begin
if (signal == 1) begin
trig_counter <= trig_counter + 1;
end else begin
if (trig_counter >= TRIG_PULSE_CYCLES-2 && trig_counter <= TRIG_PULSE_CYCLES+2) begin
valid_trig <= 1;
end else begin
valid_trig <= 0;
end
end
end
end
reg [15:0] echo_delay_counter;
always @(posedge clk) begin
if (state == S_SEND_ECHO) begin
if (echo_delay_counter == 5800) begin //
signal_out <= 0;
echo_sended <= 1;
end else begin
signal_out <= 1;
echo_delay_counter <= echo_delay_counter + 1;
end
end else begin
echo_delay_counter <= 0;
end
end
endmodule