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TX tested with other's rx code (its work)

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Gamenight77
2025-05-05 09:26:41 +02:00
parent f5e73d7379
commit c9a5fba97e
6 changed files with 220 additions and 237 deletions
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24
Semaine_4/UART/src/verilog/uart_tx.v
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@@ -5,10 +5,10 @@ module uart_tx #(
input wire clk,
input wire rst_p,
input wire[7:0] data,
input wire tx_data_valid,
input wire tx_enable,
output wire tx,
output reg tx_data_ready
output reg tx_ready,
output wire tx
);
localparam CYCLE = CLK_FREQ / BAUD_RATE;
@@ -38,7 +38,7 @@ module uart_tx #(
always@(*) begin
case(state)
IDLE:
if(tx_data_valid == 1'b1)
if(tx_enable == 1'b1)
next_state = START;
else
next_state = IDLE;
@@ -65,17 +65,17 @@ module uart_tx #(
endcase
end
always@(posedge clk or posedge rst_p)begin // tx_data_ready block
always@(posedge clk or posedge rst_p)begin // tx_ready block
if(rst_p == 1'b1)
tx_data_ready <= 1'b0; // Reset
else if(state == IDLE && tx_data_valid == 1'b1)
tx_data_ready <= 1'b0; // Pas prêt tant que les données sont valides
tx_ready <= 1'b0; // Reset
else if(state == IDLE && tx_enable == 1'b1)
tx_ready <= 1'b0; // Pas prêt tant que les données sont valides
else if(state == IDLE)
tx_data_ready <= 1'b1;
tx_ready <= 1'b1;
else if(state == STOP && cycle_cnt == CYCLE - 1)
tx_data_ready <= 1'b1; // Prêt une fois le bit STOP envoyé
tx_ready <= 1'b1; // Prêt une fois le bit STOP envoyé
else
tx_data_ready <= tx_data_ready; // Reste inchangé dans d'autres cas
tx_ready <= tx_ready; // Reste inchangé dans d'autres cas
end
@@ -83,7 +83,7 @@ module uart_tx #(
always@(posedge clk or posedge rst_p) begin // tx_data_latch block
if(rst_p == 1'b1) begin
tx_data_latch <= 8'd0;
end else if(state == IDLE && tx_data_valid == 1'b1) begin
end else if(state == IDLE && tx_enable == 1'b1) begin
tx_data_latch <= data; // Charger les données de `data` dans `tx_data_latch`
end
end