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TX tested with other's rx code (its work)

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Gamenight77
2025-05-05 09:26:41 +02:00
parent f5e73d7379
commit c9a5fba97e
6 changed files with 220 additions and 237 deletions
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54
Semaine_4/UART/tests/verilog/tb_uart_tx.v
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@@ -3,44 +3,68 @@
module tb_uart_tx;
reg clk = 0;
reg start = 0;
reg [7:0] data = 8'h00;
reg tx_enable = 0;
reg [7:0] data_in = 8'h00;
reg [7:0] data_out;
wire tx;
wire busy;
reg tx_ready;
wire rx_recieved;
always #18.5 clk = ~clk;
uart_rx rx_instance(
.clk(clk),
.rx_pin(tx), // tx is connected to rx for testing
.rst_n(1'b1),
.rx_data(data_out),
.rx_data_valid(rx_recieved),
.rx_data_ready(1'b1)
);
uart_tx #(
.CLK_FREQ(27_000_000),
.BAUD_RATE(115_200)
)tx_instance (
.clk(clk),
.start(start),
.data(data),
.tx_enable(tx_enable),
.tx_ready(tx_ready),
.data(data_in),
.tx(tx),
.busy(busy)
.rst_p(1'b0)
);
initial begin
$dumpfile("uart_tx.vcd");
$dumpfile("runs/uart_tx.vcd");
$dumpvars(0, tb_uart_tx);
#100;
data <= 8'hA5; // 10100101 0xA5
start <= 1;
#37 start <= 0;
data_in <= 8'd234; // 234
tx_enable <= 1;
wait(tx_ready == 1'b0);
tx_enable <= 0;
// Attendre
wait (busy == 0);
wait (rx_recieved == 1'b1); // Attendre que le signal de reception soit actif
$display("Data received: %d", data_out); // Afficher la valeur recu
$display("Data expected: %d", data_in); // Afficher la valeur envoyee
#1000;
data <= 8'h3C; // 00111100 0x3C
start <= 1;
#37 start <= 0;
wait(tx_ready == 1'b1); // Attendre que le signal de reception soit actif
wait (busy == 0);
data_in <= 8'd202; // 202
tx_enable <= 1;
wait(tx_ready == 1'b0);
tx_enable <= 0;
// Attendre
wait (rx_recieved == 1'b1); // Attendre que le signal de reception soit actif
$display("Data received: %d", data_out); // Afficher la valeur recu
$display("Data expected: %d", data_in); // Afficher la valeur envoyee
#1000;
$stop;