From cac1a38dad895da953aa38e1373fcf78e25bcbd2 Mon Sep 17 00:00:00 2001
From: tanchou <louis.tanchou@gmail.com>
Date: Mon, 26 May 2025 11:18:25 +0200
Subject: [PATCH] Leds

---
 .../DHT11_UART/constraints/dht11_uart_top.cst | 14 +++++++++
 Semaine_7/DHT11_UART/scripts/linux/build.sh   |  2 +-
 .../DHT11_UART/src/verilog/dht11_uart_top.v   | 10 ++++++-
 .../DHT11_UART/tests/pyhton/readSerial.py     | 30 +++++++++++++++++++
 4 files changed, 54 insertions(+), 2 deletions(-)
 create mode 100644 Semaine_7/DHT11_UART/tests/pyhton/readSerial.py

diff --git a/Semaine_7/DHT11_UART/constraints/dht11_uart_top.cst b/Semaine_7/DHT11_UART/constraints/dht11_uart_top.cst
index 14bc549..be9430f 100644
--- a/Semaine_7/DHT11_UART/constraints/dht11_uart_top.cst
+++ b/Semaine_7/DHT11_UART/constraints/dht11_uart_top.cst
@@ -6,3 +6,17 @@ IO_PORT "clk" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
 
 IO_LOC "io_dht11_sig" 73;
 IO_PORT "io_dht11_sig" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+
+
+IO_LOC "leds[0]" 15;
+IO_PORT "leds[0]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
+IO_LOC "leds[1]" 16;
+IO_PORT "leds[1]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
+IO_LOC "leds[2]" 17;
+IO_PORT "leds[2]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
+IO_LOC "leds[3]" 18;
+IO_PORT "leds[3]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
+IO_LOC "leds[4]" 19;
+IO_PORT "leds[4]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
+IO_LOC "leds[5]" 20;
+IO_PORT "leds[5]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
\ No newline at end of file
diff --git a/Semaine_7/DHT11_UART/scripts/linux/build.sh b/Semaine_7/DHT11_UART/scripts/linux/build.sh
index 3d697c0..dd0e9c7 100644
--- a/Semaine_7/DHT11_UART/scripts/linux/build.sh
+++ b/Semaine_7/DHT11_UART/scripts/linux/build.sh
@@ -37,7 +37,7 @@ if [ $? -ne 0 ]; then
 fi
 
 echo "=== Étape 4 : Flash avec openFPGALoader ==="
-openFPGALoader -b "$BOARD" "$BITSTREAM"
+sudo /etc/oss-cad-suite/bin/openFPGALoader -b "$BOARD" "$BITSTREAM"
 if [ $? -ne 0 ]; then
   echo "=== Erreur lors du flash ==="
   exit 1
diff --git a/Semaine_7/DHT11_UART/src/verilog/dht11_uart_top.v b/Semaine_7/DHT11_UART/src/verilog/dht11_uart_top.v
index fa066b5..b048f95 100644
--- a/Semaine_7/DHT11_UART/src/verilog/dht11_uart_top.v
+++ b/Semaine_7/DHT11_UART/src/verilog/dht11_uart_top.v
@@ -2,7 +2,8 @@
 module dht11_uart_top (
     input clk,
     inout io_dht11_sig,
-    output tx
+    output tx,
+    output reg [5:0] leds
 );
 
 localparam CLK_FREQ = 27_000_000; // 27 MHz
@@ -58,6 +59,8 @@ always_ff @(posedge clk) begin
         delay_counter <= delay_counter + 1;
         strobe2s <= 0;
     end
+
+    leds[5] <= o_dht11_error;
 end
 
 always_ff @(posedge clk) begin
@@ -67,6 +70,7 @@ always_ff @(posedge clk) begin
             wr_en <= 1;
             wr_data <= data_fifo;
             state <= WAIT;
+            leds [4:0] = 5'b11110;
         end
         WAIT: begin
             i_start <= 0;
@@ -75,6 +79,7 @@ always_ff @(posedge clk) begin
                 state <= MESURE;
                 i_start <= 1;
             end
+            leds [4:0] = 5'b11100;
         end
 
         MESURE: begin
@@ -84,17 +89,20 @@ always_ff @(posedge clk) begin
                 wr_data <= o_temp_data;
                 wr_en <= 1;
             end
+            leds [4:0] = 5'b11000;
         end
 
         SEND_FIFO1: begin
             wr_data <= o_hum_data;
             wr_en <= 1;
             state <= SEND_FIFO2;
+            leds [4:0] = 5'b10000;
         end
 
         SEND_FIFO2: begin
             wr_en <= 0;
             state <= WAIT;
+            leds [4:0] = 5'b00000;
         end
 
         default: state <= WAIT;
diff --git a/Semaine_7/DHT11_UART/tests/pyhton/readSerial.py b/Semaine_7/DHT11_UART/tests/pyhton/readSerial.py
new file mode 100644
index 0000000..8851635
--- /dev/null
+++ b/Semaine_7/DHT11_UART/tests/pyhton/readSerial.py
@@ -0,0 +1,30 @@
+import serial
+import time
+
+# Configuration du port série
+ser = serial.Serial(
+    port='/dev/ttyUSB0',  # Remplace par ton port (ex : COM3 sous Windows)
+    baudrate=115200,
+    timeout=1  # En secondes
+)
+
+print("Lecture du port série... (Ctrl+C pour quitter)")
+
+try:
+    while True:
+        # Lire 2 octets
+        data = ser.read(2)
+
+        if len(data) == 2:
+            temperature = data[0]
+            humidite = data[1]
+            print(f"Température: {temperature}°C, Humidité: {humidite}%")
+        else:
+            print("Pas assez de données reçues.")
+
+        time.sleep(1)
+
+except KeyboardInterrupt:
+    print("\nArrêt du script.")
+finally:
+    ser.close()