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forked from tanchou/Verilog

Add DHT11 interface and model, update testbench and scripts for simulation

This commit is contained in:
2025-05-20 15:55:21 +02:00
parent b3e646d854
commit cbebf620d5
16 changed files with 637 additions and 0 deletions

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#!/bin/bash
echo "=== Simulation avec Icarus Verilog ==="
OUT="runs/sim.vvp"
TOP="tb_dht11"
DIRS=("src/verilog" "tests/verilog")
FILES=()
for dir in "${DIRS[@]}"; do
for file in "$dir"/*.v; do
FILES+=("$file")
done
done
iverilog -g2012 -o "$OUT" -s "$TOP" "${FILES[@]}"
vvp "$OUT"